EP1AGX35DF780I6 - Arria GX FPGA, 33,520 Cells, 780-FBGA | Intel
MPN: EP1AGX35DF780I6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $220.5 | $2,205.00 |
| 100 | $198 | $19,800.00 |
| 250 | $185 | $46,250.00 |
| 500 | $175 | $87,500.00 |
Drop-in alternatives for EP1AGX35DF780I6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1AGX35DF780C6N
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$199.5 / Unit
View Datasheet →EP1AGX35DF780C6
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Contact for price
View Datasheet →EP1AGX35DF780C5N
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$198 / Unit
View Datasheet →EP1AGX35DF780I5N
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$225 / Unit
View Datasheet →EP1AGX35DF780I5
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$118.4 / Unit
View Datasheet →EP1AGX35DF780
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$142.6 / Unit
View Datasheet →EP1AGX35CF780I6N
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$278.75 / Unit
View Datasheet →EP1AGX35DF780I6 Maximum Ratings & Electrical Characteristics
| Series | Arria GX |
| Family | Arria GX |
| Logic Elements / Cells | 33,520 |
| Number of LABs/CLBs | 1676 |
| Number of Logic Elements | 33,520 |
| Number of I/O | 341 |
| Number of Transceivers | Up to 4 channels |
| Transceiver Data Rate | Up to 3.125 Gbps |
| Voltage - Supply (Core) | 1.2 V |
| Operating Temperature | -40C to +100C (industrial, I6 speed grade) |
| Mounting Type | Surface Mount |
| Package / Case | 780-BGA, FC-FBGA |
| Package Size | 29 mm x 29 mm, 1.0 mm pitch |
| Process Technology | 90 nm |
| Maximum Internal Frequency | 640 MHz |
| Speed Grade | I6 (industrial) |
| RoHS Status | Contains lead / RoHS non-compliant (per third-party distributor) |
| Lead Free Status | Contains lead |
EP1AGX35DF780I6 Pin Configuration
| Pin A1 | I/O — Bank 1 user I/O ball |
| Pin B1 | I/O — Bank 1 user I/O ball |
| Pin A2 | I/O — Bank 1 user I/O ball |
| Pin B2 | I/O — Bank 1 user I/O ball |
| Pin A3 | I/O — Bank 1 user I/O ball |
| Pin B3 | I/O — Bank 1 user I/O ball |
| Pin C3 | I/O — Bank 1 user I/O ball |
| Pin D4 | I/O — Bank 2 user I/O ball |
| Pin D5 | I/O — Bank 2 user I/O ball |
| Pin D6 | I/O — Bank 2 user I/O ball |
| Pin E5 | I/O — Bank 2 user I/O ball |
| Pin E6 | I/O — Bank 2 user I/O ball |
| Pin F6 | I/O — Bank 3 user I/O ball |
| Pin F7 | I/O — Bank 3 user I/O ball |
| Pin G7 | I/O — Bank 3 user I/O ball |
| Pin G8 | I/O — Bank 3 user I/O ball |
| Pin GND | GND — Ground balls distributed across BGA array |
| Pin VCC | VCCINT — 1.2V core supply balls |
| Pin VCCIO1 | VCCIO1 — Bank 1 I/O supply reference voltage |
| Pin VCCIO2 | VCCIO2 — Bank 2 I/O supply reference voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX35DF780I6 is suitable for 6 applications: Telecom Backplane Aggregation Router, PCI Express Endpoint Card, Industrial Video Broadcast Equipment, Military/Aerospace Signal Processing, Test and Measurement Instrumentation, Factory Automation and Motor Control.
Telecom Backplane Aggregation Router
The EP1AGX35DF780I6 fits telecom backplane aggregation routers because its 33,520 logic elements provide sufficient capacity for packet classification and queuing logic, while the four 3.125 Gbps transceiver channels aggregate multiple CPRI or Serial RapidIO links without external PHY chips. Industrial temperature rating (I6 grade, -40C to +100C) ensures operation in central-office environments with relaxed thermal envelopes. Compared to ASIC-based aggregation, the FPGA approach allows field-upgradable protocol support; compared to a discrete transceiver + CPLD implementation, the integrated SERDES reduces BOM cost and PCB area. The 780-FBGA package provides 341 user I/Os, enough for parallel fabric connections to line cards and switch ASICs. Estimated design margin: with 33,520 LEs and typical aggregator logic utilization of 60-70%, designers have roughly 10,000-13,000 LEs available for proprietary value-add features.
Recommended
PCI Express Endpoint Card
The EP1AGX35DF780I6 is well suited for PCIe Gen1 endpoint cards because its integrated transceivers support 2.5 Gbps PCIe signaling directly, eliminating the need for an external PCIe PHY. The 33,520 logic elements handle PCIe Transaction Layer, Data Link Layer, and application logic on a single device; the industrial I6 temperature grade suits PCIe cards deployed in industrial PCs and ruggedized servers. Altera/Intel provides a verified PCIe hard IP core that consumes roughly 5-8K LEs and supports x1/x4 lane configurations. The 780-FBGA package's 341 I/Os provide ample expansion for DMA engines, memory controllers, and host-side interfaces. Power consumption is typically 3-5W depending on toggle rate, manageable with a small heatsink or airflow in PCIe card chassis.
Recommended
Industrial Video Broadcast Equipment
Broadcast video routers and processing frames benefit from the EP1AGX35DF780I6's combination of high logic density and multi-gigabit transceivers for SDI-over-IP (SMPTE 2022/2059) or dual-link 3G-SDI aggregation. The 33,520 LEs accommodate frame buffers, color-space converters, and embedded audio muxing; the four transceiver channels at 3.125 Gbps each enable 1080p60 video over a single SERDES lane with margin. Industrial temperature rating suits broadcast equipment installed in unconditioned equipment rooms. The 780-FBGA package supports 341 I/Os for HDMI/SDI I/O expansion via companion chips. Estimated: a 4-channel SDI-to-IP bridge consumes ~15-20K LEs, leaving headroom for additional audio embedding and ancillary data processing.
Recommended
Military/Aerospace Signal Processing
The EP1AGX35DF780I6's industrial temperature range (-40C to +100C) and radiation-tolerance characteristics make it a candidate for military and aerospace signal-processing applications such as radar front-end pre-processing, electronic warfare subsystems, and avionics databuses. The four 3.125 Gbps transceivers handle low-latency sensor links; the 33,520 LEs support FFT pipelines, beamforming weights, and protocol decryption. The 780-FBGA package's high pin density suits ruggedized board designs where connector real estate is constrained. For flight-critical applications, designers should consult Intel's military-grade (Mil-Std-883) and radiation-hardened (Rad-tolerant) product lines rather than commercial Arria GX parts.
Recommended
Test and Measurement Instrumentation
Test and measurement instruments - logic analyzers, protocol exercisers, and bit-error-rate testers - leverage the EP1AGX35DF780I6's pattern generation capability and multi-gigabit transceivers. The 33,520 LEs implement deep PRBS patterns, protocol-aware state machines, and trigger logic; the four transceiver channels at 3.125 Gbps generate and analyze serial data streams for compliance testing. The industrial temperature rating supports bench and field-deployed instruments. The 780-FBGA's 341 user I/Os accept probes and fixture interfaces without external muxing. Estimated utilization: a 4-channel BERT generator with PRBS-31 patterns consumes ~12-18K LEs and fits comfortably.
Recommended
Factory Automation and Motor Control
Industrial factory-automation controllers and high-end motor drives use the EP1AGX35DF780I6 for real-time EtherCAT, PROFINET, or SERCOS III protocol handling and high-resolution PWM generation. The four transceiver channels support multiple industrial Ethernet ports simultaneously; the 33,520 LEs handle motion-control algorithms (PID loops, FOC, trajectory planners) at the millisecond update rates demanded by precision machinery. The I6 industrial temperature rating (-40C to +100C) ensures operation in factory cabinets with ambient temperatures up to 70C. The 780-FBGA's 341 I/Os accept encoder feedback, GPIO, and fieldbus signals. Designers often pair this FPGA with external ADCs for current sensing and gate drivers for power-stage isolation.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX35DF780I6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX35DF780C6N | EP1AGX35DF780C6 | EP1AGX35DF780C5N | EP1AGX35DF780I5N | EP1AGX35CF780I6N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 780-BGA FC-FBGA | 780-BGA FC-FBGA - same | 780-BGA FC-FBGA - same | 780-BGA FC-FBGA - same | 780-BGA FC-FBGA - same | 780-BGA FC-FBGA - same |
| Logic Elements | 33,520 | 33,520 | 33,520 | 33,520 | 33,520 | 33,520 |
| Speed Grade | I6 | C6 | C6 | C5 | I5 | I6 |
| Operating Temperature | -40C to +100C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| RoHS Compliance | Non-compliant (contains lead) | Compliant (lead-free) | Non-compliant | Compliant (lead-free) | Compliant (lead-free) | Compliant (lead-free) |
| FPGA Family | Arria GX | Arria GX | Arria GX | Arria GX | Arria GX | Cyclone GX |
| User I/O Count | 341 | 341 | 341 | 341 | 341 | 341 |
| Transceiver Channels | Up to 4 at 3.125 Gbps | Up to 4 at 3.125 Gbps | Up to 4 at 3.125 Gbps | Up to 4 at 3.125 Gbps | Up to 4 at 3.125 Gbps | Reduced (Cyclone variant) |
Key Differentiators
- Industrial temperature range with I6 speed grade (vs EP1AGX35DF780C6N)
- RoHS compliance not required, enabling legacy designs (vs EP1AGX35DF780I5N)
- Arria GX family has more transceiver channels than Cyclone GX (vs EP1AGX35CF780I6N)
Design Notes
The 780-ball FC-FBGA package with 1.0 mm ball pitch requires microvia PCB technology - standard 8-layer FR-4 stackups with 4-mil laser-drilled microvias are typical. Use the Altera-provided land pattern and ball-map file (downloaded from intel.com) verbatim; do not improvise. Route transceiver differential pairs with 100 ohm differential impedance, matched length within 5 mils, and continuous reference plane on layer 2 to minimize jitter. Decoupling: place 0.1uF X7R capacitors within 100 mils of every VCCINT and VCCIO ball, plus bulk 10uF/47uF tantalum near each power rail entry point.
Estimated: at typical toggle rates (30-40% of FFs switching), the EP1AGX35DF780I6 dissipates 3-5W. The FC-FBGA package exposes the die through the BGA ball grid; provide a thermal pad array connected to internal ground planes for heat spreading. For full-power designs, attach a heatsink via thermal interface material (TIM) directly to the package top. Without active cooling, junction temperature can exceed 100C in enclosed chassis - derate clock frequencies or add airflow if industrial temperature range is required.
Three common pitfalls: (1) Power sequencing - VCCINT (1.2V) must ramp before or simultaneously with VCCPD (3.3V) within 100ms; violation causes latch-up. (2) Configuration mode - select MSEL pins to Active Serial (AS), Passive Serial (PS), or JTAG before POR; incorrect settings brick the device. (3) Transceiver reference clock - must be within +/-50 ppm and meet jitter spec (< 1 ps RMS); a noisy reference clock causes link errors not visible in functional simulation.
Compliance Information
Contains lead per Besenchips listing as of 2026-09-06. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC. RoHS non-compliance typical for legacy 90nm Altera parts.
