EP1AGX35DF780 - Arria GX FPGA, 35K LE, 780-BGA | Altera / Intel
MPN: EP1AGX35DF780 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $217.14 | $217.14 |
| 10 | $195.43 | $1,954.30 |
| 100 | $173.71 | $17,371.00 |
| 250 | $158.2 | $39,550.00 |
| 500 | $142.6 | $71,300.00 |
Drop-in alternatives for EP1AGX35DF780 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1AGX35CF780I6N
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View Datasheet →EP1AGX20CF780I6N
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View Datasheet →EP1AGX20CF780C6N
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View Datasheet →EP1AGX20CF780C5N
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View Datasheet →EP1AGX20CF780I6
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View Datasheet →EP1AGX35DF780 Maximum Ratings & Electrical Characteristics
| Series | Arria GX |
| Family | Altera Arria GX (90 nm) |
| Logic Elements (LE) | 33,520 |
| Embedded Memory | 1,348,416 bits (1.34 Mbit) |
| Maximum User I/Os | 341 |
| Number of LABs / CLBs | 1676 LABs |
| Transceivers | Up to 8 channels, 3.125 Gbps per channel |
| PLLs | 4 |
| Embedded Multipliers | 18x18-bit hard multipliers (DSP blocks) |
| External Memory Support | DDR, DDR2, QDRII, QDRII+ |
| Package | 780-ball FineLine BGA (FCBGA, 29x29 mm) |
| Configuration Methods | Passive Serial (PS), Fast Passive Parallel (FPP), JTAG 1149.1 |
| Operating Temperature Range | -40C to +85C (industrial grade I-suffix variants available) |
| Process Node | 90 nm CMOS |
| RoHS Status | Compliant (lead-free variant) |
| Lifecycle | Mature / Obsolete in Intel FPGA product tree |
EP1AGX35DF780 780-ball fineline bga (fcbga, 29x29 mm) Pin Configuration Guide
Complete pinout information for EP1AGX35DF780 (780-ball fineline bga (fcbga, 29x29 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX35DF780.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX35DF780 is suitable for 6 applications: Telecom Backplane Aggregation, Broadcast Video Routing and SDI Switching, PCI Express Endpoint Cards, High-Speed Data Acquisition Front-Ends, Industrial Protocol Bridging, Wireless Baseband Processing.
Telecom Backplane Aggregation
The EP1AGX35DF780's 8 channels of 3.125 Gbps transceivers are a direct fit for telecom backplane aggregation cards that consolidate multiple lower-speed tributary links into a higher-speed uplink. Its 33,520 logic elements, 1.34 Mbit embedded RAM, and 341 user I/Os provide ample headroom to implement cross-connect logic, packet buffering, and SERDES adaptation in a single device - eliminating the cost and board area of an external PHY. The hard PCS/PMA also supports protocols like Serial RapidIO and Interlaken natively.
Recommended
Broadcast Video Routing and SDI Switching
Studio and broadcast video routers need to switch SD-SDI (270 Mbps), HD-SDI (1.485 Gbps), and 3G-SDI (2.97 Gbps) streams between many sources and destinations. The EP1AGX35DF780's transceiver channels handle SDI natively at standard rates, while its 33K logic elements, embedded multipliers, and 1.34 Mbit RAM implement genlocking, audio de-embedding, and matrix-switching fabric. Industrial temperature variants qualify the part for 24/7 broadcast-facility operation where downtime is unacceptable.
Recommended
PCI Express Endpoint Cards
With native 3.125 Gbps transceivers, the EP1AGX35DF780 implements PCIe Gen1 x1/x4 endpoints without external PHY chips, cutting BOM cost and board area. Its 33K logic elements host a soft PCIe IP core plus application payload, while the 1.34 Mbit embedded RAM serves as a transaction buffer for DMA engines. Industrial-grade variants suit ruggedized server cards, industrial PCs, and instrumentation add-in boards where extended temperature operation is required.
Recommended
High-Speed Data Acquisition Front-Ends
Test-and-measurement digitizers and oscilloscope front-ends need multi-gigabit serial links to stream ADC data to a host processor. The EP1AGX35DF780 pairs its 3.125 Gbps transceivers with hard multipliers (for FIR decimation filters), 1.34 Mbit embedded RAM (for sample buffering), and 341 user I/Os (to interface LVDS ADCs). The industrial temperature grade makes it suitable for bench, ATE, and field-portable instruments that must operate across wide thermal ranges.
Recommended
Industrial Protocol Bridging
Factory automation gateways must bridge legacy fieldbuses (Profibus, RS-485, CAN) to modern Ethernet/IP and EtherCAT networks. The EP1AGX35DF780's high-speed transceivers handle Ethernet PHY duties, while its abundant logic implements soft-core CPUs (Nios II) for protocol translation, 1.34 Mbit RAM buffers packets, and 341 user I/Os drive multiple fieldbus interfaces simultaneously. Industrial-grade parts ensure reliable operation in 50C cabinet environments with high EMI.
Recommended
Wireless Baseband Processing
Small-cell and pico-cell baseband designs use mid-range FPGAs like the EP1AGX35DF780 for CPRI front-haul, digital up/down-conversion, and channel-card aggregation. The 8 transceivers carry CPRI up to 3.072 Gbps, the 18x18 multipliers perform crest-factor reduction and digital pre-distortion, and the 1.34 Mbit RAM stages buffers between PHY and baseband DSP. Migration to Arria II GX (40 nm) reduces power per channel by ~40%, critical for outdoor radio units.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX35DF780 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX35CF780I6N | EP1AGX20CF780I6N | EP1AGX20CF780C6N | EP1AGX20CF780C5N | EP1AGX20CF780I6 |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | 780-ball FineLine BGA (FCBGA) | 780-ball FineLine BGA (FCBGA) | 780-ball FineLine BGA (FCBGA) | 780-ball FineLine BGA (FCBGA) | 780-ball FineLine BGA (FCBGA) | 780-ball FineLine BGA (FCBGA) |
| Logic Elements | 33,520 | 33,500 | 20,060 | 20,060 | 20,060 | 20,060 |
| Embedded Memory | 1,348,416 bits (1.34 Mbit) | [DATA_NEEDED] | ~1.05 Mbit | ~1.05 Mbit | ~1.05 Mbit | ~1.05 Mbit |
| Transceivers / Speed | 8 ch @ 3.125 Gbps | 8 ch @ 3.125 Gbps | 8 ch @ 3.125 Gbps | 8 ch @ 3.125 Gbps | 8 ch @ 3.125 Gbps | 8 ch @ 3.125 Gbps |
| Process Node | 90 nm | 40 nm | 40 nm | 40 nm | 40 nm | 40 nm |
| Operating Temperature | 0C to +85C (commercial C6) | -40C to +100C (industrial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Lifecycle Status | Obsolete (Arria GX EOL) | Obsolete (Arria II GX) | Obsolete (Arria II GX) | Obsolete (Arria II GX) | Obsolete (Arria II GX) | Obsolete (Arria II GX) |
| RoHS | Compliant (N suffix) | Compliant (N suffix) | Compliant (N suffix) | Compliant (N suffix) | Compliant (N suffix) | Non-RoHS (no N suffix) |
Key Differentiators
- Highest logic density in the Arria GX 780-FBGA family (vs EP1AGX20CF780I6N)
- Arria II GX (40 nm) migration available in same 780-BGA footprint (vs EP1AGX35CF780I6N)
- Industrial temperature variants available for harsh environments (vs EP1AGX20CF780C6N)
Design Notes
Estimated: at full transceiver utilization (8 channels @ 3.125 Gbps) and 75% logic toggling, junction power can exceed 5 W. The 780-ball FCBGA (29x29 mm) has theta_JA in the 15-20 C/W range on a JEDEC 4-layer test board, requiring at least a moderate copper pour or a heatsink for industrial-temperature operation. Use the Altera PowerPlay Early Power Estimator before RTL completion to budget thermal dissipation and validate regulator sizing. Always apply thermal interface material (TIM) if a discrete heatsink is used.
The 780-ball FCBGA uses a 1.0 mm ball pitch - the PCB must follow IPC-7351 land-pattern guidelines and use NSMD (non-solder-mask-defined) pads for best joint reliability. Stack-up should specify 4-6 mil laser-drilled microvias for breakout and a continuous GND plane on layer 2 to provide return paths for high-speed transceivers. Per JEDEC J-STD-020, the device is MSL3 (30C/60% RH floor life 168 hours) - bake-out is required if the factory floor exposure exceeds that window.
Transceiver channels require 100-ohm differential pairs routed with controlled impedance (typically 85-ohm on inner stripline layers, 90-ohm on microstrip) and length matching to within 5 mils within a channel and 50 mils across a group for protocols like PCIe. Keep AC-coupling capacitors close to the transmitter pins and provide solid GND return stitching vias every 200 mils along the trace route to minimize EMI and signal-integrity issues.
Do not assume the EP1AGX35DF780 can be hot-swapped or live-updated without verifying configuration scheme support. When migrating to Arria II GX (40 nm) on the same 780-BGA footprint, double-check pinout compatibility via the Altera pin migration tool - while the high-level ball map is similar, several transceiver supply pins and JTAG pin assignments changed between the two generations, and a naive swap will short power rails.
Estimated: VCCINT (core) typically 1.2 V and VCCIO (I/O banks) at 1.5/1.8/2.5/3.3 V depending on bank assignment. Always sequence supplies per Altera's recommended power-up sequence - VCCINT before VCCAUX before VCCIO - to prevent latch-up during board power ramp. Decouple each supply pin with 0.1 uF X7R ceramic placed within 100 mils, plus bulk decoupling of 10-100 uF tantalum or polymer per supply rail.
Compliance Information
RoHS compliance applies to 'N' suffix variants. AEC-Q100 not applicable - this is an industrial/communications FPGA, not an automotive-qualified part. Halogen-free status not published in distributor data.
