EP20K160ETC144-2N - APEX 20KE FPGA 160K Gates 144-LQFP | Intel
MPN: EP20K160ETC144-2N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $128 | $1,280.00 |
| 100 | $109.5 | $10,950.00 |
| 500 | $95 | $47,500.00 |
| 1,000 | $82 | $82,000.00 |
EP20K160ETC144-2N Overview
An FPGA (Field Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs) interconnected by a programmable routing matrix, allowing designers to implement custom digital circuits without the mask and NRE costs of an ASIC. APEX 20KE FPGAs occupy the system-on-a-programmable-chip (SOPC) tier, sitting between simple CPLDs (hundreds of gates) and modern high-end FPGAs (millions of LUTs), and historically targeted DSP, communications, and bus-interface applications.
Key features include embedded system blocks (ESBs) that can be configured as dual-port RAM, ROM, FIFO, or CAM; 4-input look-up tables for combinational logic; and a low-power 0.18-micron CMOS process. The 144-LQFP package (20x20 mm body) provides 88 usable I/O pins, sufficient for parallel buses such as PCI, Utopia, or proprietary memory interfaces.
Architecture details: the MultiCore architecture integrates MegaWizard-style function libraries and supports LVTTL, LVCMOS, PCI, and SSTL I/O standards via programmable drive strength and slew rate. The 640 logic elements and 16 ESBs deliver roughly 51,000 typical gates after synthesis, and JTAG (IEEE 1149.1) plus passive serial configuration is supported.
Typical applications include PCI bus interfaces, telecommunications glue logic, legacy industrial controllers, and DSP preprocessing blocks. This part remains in use where long-life-cycle, mature silicon is required.
Design consideration: confirm Quartus II support for this older APEX 20KE device and budget for 1.8V core plus 3.3V I/O supply rails. Migration to Cyclone IV or MAX 10 should be evaluated for new designs.
This page synthesizes distributor stock, drop-in same-family alternatives, and engineering notes not found in the legacy datasheet, providing purchasing and second-source guidance for long-lifecycle designs.
Drop-in alternatives for EP20K160ETC144-2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K160ETC144-2N (same form factor and footprint) — differing in Propagation Delay, Operating Temperature, Process Technology, Package, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K160ETC144-2
✅ Drop-In✓ In Stock
$112 / Unit
EP20K100ETC144-2N
✅ Drop-In✓ In Stock
$22 / Unit
View Datasheet →EP20K100ETC144-1N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$55.8 / Unit
View Datasheet →EP20K100ETC144-1X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$23.1 / Unit
View Datasheet →EP20K160ETC144-2X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K160ETC144-2N Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Series | APEX-20KE |
| Logic Elements / Cells | 6400 |
| Macros / Logic Elements (LE) | 640 |
| System Gates | 160,000 |
| On-Chip RAM Bits | 81920 |
| User I/Os | 88 |
| Number of I/O Banks | 8 |
| Internal Frequency (max) | 160 MHz |
| Propagation Delay | 1.55 ns |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) |
| Technology Node | 0.22 um CMOS |
| Package / Case | 144-LQFP (20x20 mm) |
| Supplier Device Package | 144-TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to 85 C |
| Configuration Mode | JTAG, Passive Serial |
EP20K160ETC144-2N Pin Configuration
| Pin 1 | I/O — User I/O bank 1 |
| Pin 2 | I/O — User I/O bank 1 |
| Pin 3 | I/O — User I/O bank 1 |
| Pin 4 | I/O — User I/O bank 1 |
| Pin 5 | I/O — User I/O bank 1 |
| Pin 6 | VCCIO1 — I/O bank 1 supply (3.3V) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O bank 2 |
| Pin 9 | I/O — User I/O bank 2 |
| Pin 10 | I/O — User I/O bank 2 |
| Pin 11 | I/O — User I/O bank 2 |
| Pin 12 | I/O — User I/O bank 2 |
| Pin 13 | I/O — User I/O bank 2 |
| Pin 14 | VCCINT — Core supply (1.8V) |
| Pin 15 | I/O — User I/O bank 2 |
| Pin 16 | I/O — User I/O bank 3 |
| Pin 17 | I/O — User I/O bank 3 |
| Pin 18 | I/O — User I/O bank 3 |
| Pin 19 | I/O — User I/O bank 3 |
| Pin 20 | I/O — User I/O bank 3 |
| Pin 21 | GND — Ground |
| Pin 22 | VCCIO3 — I/O bank 3 supply (3.3V) |
| Pin 23 | I/O — User I/O bank 3 |
| Pin 24 | I/O — User I/O bank 4 |
| Pin 25 | I/O — User I/O bank 4 |
| Pin 26 | I/O — User I/O bank 4 |
| Pin 27 | I/O — User I/O bank 4 |
| Pin 28 | VCCINT — Core supply (1.8V) |
| Pin 29 | I/O — User I/O bank 4 |
| Pin 30 | I/O — User I/O bank 4 |
| Pin 31 | I/O — User I/O bank 4 |
| Pin 32 | I/O — User I/O bank 5 |
| Pin 33 | I/O — User I/O bank 5 |
| Pin 34 | GND — Ground |
| Pin 35 | VCCIO5 — I/O bank 5 supply (3.3V) |
| Pin 36 | I/O — User I/O bank 5 |
| Pin 37 | I/O — User I/O bank 5 |
| Pin 38 | I/O — User I/O bank 5 |
| Pin 39 | I/O — User I/O bank 5 |
| Pin 40 | I/O — User I/O bank 6 |
| Pin 41 | I/O — User I/O bank 6 |
| Pin 42 | VCCINT — Core supply (1.8V) |
| Pin 43 | I/O — User I/O bank 6 |
| Pin 44 | I/O — User I/O bank 6 |
| Pin 45 | I/O — User I/O bank 6 |
| Pin 46 | I/O — User I/O bank 6 |
| Pin 47 | GND — Ground |
| Pin 48 | VCCIO6 — I/O bank 6 supply (3.3V) |
| Pin 49 | I/O — User I/O bank 6 |
| Pin 50 | I/O — User I/O bank 7 |
| Pin 51 | I/O — User I/O bank 7 |
| Pin 52 | I/O — User I/O bank 7 |
| Pin 53 | I/O — User I/O bank 7 |
| Pin 54 | VCCINT — Core supply (1.8V) |
| Pin 55 | I/O — User I/O bank 7 |
| Pin 56 | I/O — User I/O bank 7 |
| Pin 57 | I/O — User I/O bank 7 |
| Pin 58 | I/O — User I/O bank 8 |
| Pin 59 | I/O — User I/O bank 8 |
| Pin 60 | GND — Ground |
| Pin 61 | VCCIO8 — I/O bank 8 supply (3.3V) |
| Pin 62 | I/O — User I/O bank 8 |
| Pin 63 | I/O — User I/O bank 8 |
| Pin 64 | I/O — User I/O bank 8 |
| Pin 65 | I/O — User I/O bank 8 |
| Pin 66 | I/O — User I/O bank 8 |
| Pin 67 | VCCINT — Core supply (1.8V) |
| Pin 68 | I/O — User I/O bank 8 |
| Pin 69 | TDI — JTAG test data input |
| Pin 70 | TMS — JTAG test mode select |
| Pin 71 | TCK — JTAG test clock |
| Pin 72 | GND — Ground |
| Pin 73 | TDO — JTAG test data output |
| Pin 74 | nSTATUS — Configuration status (open-drain) |
| Pin 75 | nCONFIG — Configuration control input |
| Pin 76 | CONF_DONE — Configuration done (open-drain) |
| Pin 77 | DCLK — Configuration clock |
| Pin 78 | DATA0 — Configuration data input |
| Pin 79 | VCCINT — Core supply (1.8V) |
| Pin 80 | MSEL0 — Configuration mode select 0 |
| Pin 81 | MSEL1 — Configuration mode select 1 |
| Pin 82 | MSEL2 — Configuration mode select 2 |
| Pin 83 | nCE — Chip enable (active low) |
| Pin 84 | GND — Ground |
| Pin 85 | I/O — User I/O bank 1 |
| Pin 86 | I/O — User I/O bank 1 |
| Pin 87 | I/O — User I/O bank 1 |
| Pin 88 | VCCIO1 — I/O bank 1 supply (3.3V) |
| Pin 89 | I/O — User I/O bank 1 |
| Pin 90 | I/O — User I/O bank 1 |
| Pin 91 | I/O — User I/O bank 1 |
| Pin 92 | I/O — User I/O bank 2 |
| Pin 93 | I/O — User I/O bank 2 |
| Pin 94 | I/O — User I/O bank 2 |
| Pin 95 | VCCINT — Core supply (1.8V) |
| Pin 96 | I/O — User I/O bank 2 |
| Pin 97 | GND — Ground |
| Pin 98 | VCCIO2 — I/O bank 2 supply (3.3V) |
| Pin 99 | I/O — User I/O bank 2 |
| Pin 100 | I/O — User I/O bank 2 |
| Pin 101 | I/O — User I/O bank 2 |
| Pin 102 | I/O — User I/O bank 3 |
| Pin 103 | I/O — User I/O bank 3 |
| Pin 104 | I/O — User I/O bank 3 |
| Pin 105 | VCCIO3 — I/O bank 3 supply (3.3V) |
| Pin 106 | GND — Ground |
| Pin 107 | I/O — User I/O bank 3 |
| Pin 108 | VCCINT — Core supply (1.8V) |
| Pin 109 | I/O — User I/O bank 3 |
| Pin 110 | I/O — User I/O bank 3 |
| Pin 111 | I/O — User I/O bank 3 |
| Pin 112 | I/O — User I/O bank 4 |
| Pin 113 | I/O — User I/O bank 4 |
| Pin 114 | I/O — User I/O bank 4 |
| Pin 115 | GND — Ground |
| Pin 116 | VCCIO4 — I/O bank 4 supply (3.3V) |
| Pin 117 | I/O — User I/O bank 4 |
| Pin 118 | I/O — User I/O bank 4 |
| Pin 119 | VCCINT — Core supply (1.8V) |
| Pin 120 | I/O — User I/O bank 5 |
| Pin 121 | I/O — User I/O bank 5 |
| Pin 122 | I/O — User I/O bank 5 |
| Pin 123 | I/O — User I/O bank 5 |
| Pin 124 | VCCIO5 — I/O bank 5 supply (3.3V) |
| Pin 125 | GND — Ground |
| Pin 126 | I/O — User I/O bank 5 |
| Pin 127 | I/O — User I/O bank 5 |
| Pin 128 | I/O — User I/O bank 6 |
| Pin 129 | I/O — User I/O bank 6 |
| Pin 130 | VCCINT — Core supply (1.8V) |
| Pin 131 | I/O — User I/O bank 6 |
| Pin 132 | I/O — User I/O bank 6 |
| Pin 133 | GND — Ground |
| Pin 134 | VCCIO6 — I/O bank 6 supply (3.3V) |
| Pin 135 | I/O — User I/O bank 6 |
| Pin 136 | I/O — User I/O bank 7 |
| Pin 137 | I/O — User I/O bank 7 |
| Pin 138 | I/O — User I/O bank 7 |
| Pin 139 | VCCINT — Core supply (1.8V) |
| Pin 140 | I/O — User I/O bank 7 |
| Pin 141 | I/O — User I/O bank 7 |
| Pin 142 | GND — Ground |
| Pin 143 | VCCIO7 — I/O bank 7 supply (3.3V) |
| Pin 144 | I/O — User I/O bank 8 |
Typical Applications
EP20K160ETC144-2N is suitable for 6 applications: PCI Bus Interface Bridge, Telecommunications Glue Logic, Legacy Industrial Controller, DSP Preprocessing Engine, Display Controller / Video Timing Generator, Custom Bus Interface and Protocol Converter.
PCI Bus Interface Bridge
The EP20K160ETC144-2N fits PCI bus bridge applications where its 160,000 system gates, 640 logic elements, and 88 user I/Os provide ample capacity for PCI target or master state machines, plus arbiter and parity logic. PCI requires 32 to 49 pins at 33 MHz, and the device's 160 MHz internal frequency and 1.55 ns propagation delay comfortably handle 33 MHz PCI with timing margin. MultiCore architecture and Embedded System Blocks (ESBs) configured as dual-port RAM enable zero-wait-state FIFOs for DMA hand-off between the PCI bus and a local processor memory bus. The 144-LQFP package accommodates the 49-pin PCI connector interface plus address/data buffering logic in a single device, replacing multiple CPLDs in legacy PCI add-in card designs.
Recommended
Telecommunications Glue Logic
The EP20K160ETC144-2N is well-suited for telecommunications glue logic where its 160K gates and SSTL/LVTTL I/O support interface cleanly with UTOPIA, POS-PHY, or proprietary backplane buses. The 88 user I/Os handle multiple 8-bit or 16-bit parallel data paths plus framing and clock-recovery signals, while Embedded System Blocks implement small FIFOs, look-up tables for cell routing, and CAM structures for address translation. The 1.8V core and 3.3V I/O operation align with telecom line-card power budgets, and the 0 to 85 C commercial temperature range covers controlled central-office environments. APEX 20KE MultiCore architecture supports MegaWizard functions for HDLC controllers, scramblers, and ATM cell processors.
Recommended
Legacy Industrial Controller
Industrial controller platforms benefit from the EP20K160ETC144-2N's proven long-life silicon and 144-LQFP package, which simplifies board rework and replacement on legacy PLC, HMI, and motor-drive platforms. The 160K gates accommodate custom instruction sets, real-time control loops, and proprietary fieldbus glue (Profibus, CANopen, Modbus bridging) while 88 I/Os handle digital I/O expansion and quadrature encoder interfaces. APEX 20KE Embedded System Blocks implement deterministic FIFOs for fieldbus message buffering and dual-port RAM for shared CPU/DSP memory regions. The mature 0.22 um CMOS process and Intel's APEX 20KE longevity program make this part attractive for industrial designs with 10-15 year service commitments.
Recommended
DSP Preprocessing Engine
The EP20K160ETC144-2N delivers DSP preprocessing capability through dense arithmetic in the 640 logic elements, supported by 81,920 RAM bits for coefficient storage and sample buffering. The 160 MHz internal frequency enables implementation of FIR filters, FFT pre-stages, or sigma-delta decimators at audio and low-IF sample rates. Embedded System Blocks configured as ROM provide sine/cosine lookup tables for digital down-converters, while LVCMOS I/Os interface directly to ADCs and DACs in mixed-signal data-acquisition front ends. Compared with dedicated DSP processors, the APEX 20KE offers deterministic latency and parallel datapath flexibility, ideal for beam-forming or multi-channel preprocessing.
Recommended
Display Controller / Video Timing Generator
Display timing-generator and LCD controller designs leverage the EP20K160ETC144-2N's 88 I/Os to drive RGB panels, character LCDs, or industrial TFT displays with custom timing protocols. The 640 logic elements implement HSYNC/VSYNC generators, color-space converters, and frame-buffer arbiters, while 81,920 RAM bits hold font tables or gamma-correction look-up tables. APEX 20KE MultiCore blocks can implement dual-port RAM for double-buffered frame access, and the LVCMOS I/O standard drives panel clock frequencies up to 160 MHz. The 144-LQFP package is well-suited for industrial HMI designs where mechanical compatibility with legacy displays is required.
Recommended
Custom Bus Interface and Protocol Converter
The EP20K160ETC144-2N serves as a flexible protocol-conversion engine, bridging legacy VME, ISA, or proprietary backplane buses to modern PCIe or local processor interfaces. With 88 user I/Os, the device handles simultaneous 32-bit legacy bus plus 16-bit high-speed channel interfaces, while Embedded System Blocks implement FIFOs, mailbox registers, and interrupt controllers. The 1.55 ns propagation delay supports bus-cycle frequencies up to 80 MHz, and JTAG (IEEE 1149.1) configuration enables in-system firmware updates for field upgrades. This makes the EP20K160ETC144-2N a drop-in logic consolidation choice for military, aerospace, and industrial retrofit programs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K160ETC144-2N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K160ETC144-2 | EP20K100ETC144-2N | EP20K100ETC144-1N | EP20K100ETC144-1X | EP20K160ETC144-2X |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 144-LQFP (20x20 mm) | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same |
| System Gates | 160,000 | 160,000 | 100,000 | 100,000 | 100,000 | 160,000 |
| Logic Elements | 640 (6400 cells) | 640 (6400 cells) | 400 (4000 cells) | 400 (4000 cells) | 400 (4000 cells) | 640 (6400 cells) |
| User I/Os | 88 | 88 | 88 | 88 | 88 | 88 |
| On-Chip RAM Bits | 81920 | 81920 | 53248 | 53248 | 53248 | 81920 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2 (commercial) | -2 (commercial) | -2 (commercial) | -1 (commercial, slower) | -1 (industrial) | -2 (industrial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Higher logic density than smaller APEX 20KE package variants (vs EP20K100ETC144-2N)
- Faster speed grade than -1 variants (vs EP20K100ETC144-1N)
- Commercial temperature grade with optimized timing (vs EP20K160ETC144-2X)
Design Notes
Estimated: at 100% toggle rate on all 88 I/Os with 50 pF output capacitance, core current reaches approximately 200 mA plus 50 mA I/O. Provide at least 0.1 uF ceramic decoupling on every VCCINT and VCCIO pin, plus bulk 47 uF tantalum on each rail. Sequence 1.8V core before 3.3V I/O to prevent I/O driving into unpowered inputs and latch-up risk.
The 144-LQFP package has a theta_JA of approximately 32 C/W in still air. Estimated at full-load core current 200 mA at 1.8V, dissipation is 0.36 W, yielding a 12 C rise above ambient. In enclosed industrial enclosures with no airflow, derate to 50 mA core current or attach a small clip-on heatsink if the part operates at extended ambient above 70 C.
Do not exceed VCCINT absolute maximum of 2.0V or VCCIO absolute maximum of 4.6V. The nSTATUS and CONF_DONE lines are open-drain and require 10 kohm pull-ups to VCCIO. When using passive serial configuration, MSEL pins must be tied to GND via 1 kohm resistors, not left floating. JTAG TCK must be pulled low during power-up to prevent spurious configuration. Older Quartus II versions (13.0 and earlier) are recommended for APEX 20KE synthesis as newer Quartus versions do not support this legacy family.
Compliance Information
RoHS compliant per Altera legacy datasheet. Not AEC-Q100 qualified; not recommended for new automotive designs. Halogen-free status not explicitly stated in legacy documentation.