Altera

EP20K30EFC144-3 - 30K APEX-20K FPGA, 144-LQFP | Intel / Altera

MPN: EP20K30EFC144-3 ✗ End of Life

In Stock Ships in 1-3 business days

1.71 V to 1.89 V Vdss 144-LQFP (20x20 mm) Package 160 MHz Speed

From $10.4 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.8	$1,380.00
500	$11.9	$5,950.00
1,000	$10.4	$10,400.00

ℹ️ All prices are in USD

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EP20K30EFC144-3 Overview

The Intel (formerly Altera) EP20K30EFC144-3 is a member of the APEX-20K family of Field Programmable Gate Arrays (FPGAs), built on a 0.22 um CMOS MultiCore architecture that integrates embedded system-on-a-programmable-chip (SOPC) blocks. The device delivers approximately 30,000 system gates with 1,200 logic elements, 24,576 bits of embedded RAM, and 92 user I/Os, housed in a 144-pin LQFP package (20x20 mm).

An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit containing an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated I/O cells. FPGAs sit within the broader taxonomy: programmable logic device (PLD) -> FPGA -> programmable logic -> digital IC -> semiconductor. The APEX-20K family combines look-up-table based logic, embedded memory (ESB), and a special-purpose MultiCore architecture that supports system-level functions such as PCI, DDR, and processor interfaces without external glue logic.

Key features of the EP20K30EFC144-3 include a 160 MHz internal operating frequency, a propagation delay of approximately 1.68 ns, support for 408 user I/O pins (varies by package - the 144-LQFP exposes 92), and a 1.8V core supply. The MultiCore architecture integrates lookup-table (LUT) logic, product-term logic, and embedded memory in a single die, allowing designers to mix datapath, state-machine, and on-chip buffering functions on one device. The "E" suffix denotes enhanced features, "FC" indicates the 144-pin LQFP package, and "-3" marks the speed grade.

Typical applications include telecommunications line cards, industrial control boards, and DSP coprocessing where a programmable logic device with embedded memory offers a more flexible alternative to fixed-function ASICs. The APEX-20K architecture supports high-speed LVDS, PCI bus interfaces, and on-chip dual-port RAM for FIFO and ping-pong buffer designs. Combined with the Quartus-II development toolchain (legacy support via MAX+PLUS II), the device remains usable in long-lifecycle systems where re-programmability is a design requirement.

Drop-in alternatives for EP20K30EFC144-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K30EFC144-3 (same form factor and footprint) — differing in Operating Temperature, Speed Grade, Family, Series, Package.

EP20K30EFC144-1

Altera

Operating Temperature: 0°C to 85°C

Speed Grade: -1 (slowest commercial)

Family: APEX-20K MultiCore