EP20K200BC356-2 - 200K Gate APEX-20K FPGA, 356-BGA | Intel
MPN: EP20K200BC356-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118.75 | $11,875.00 |
| 500 | $99.5 | $49,750.00 |
| 1,000 | $88.25 | $88,250.00 |
EP20K200BC356-2 Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be rewired after manufacturing to implement arbitrary digital logic. FPGAs sit in the programmable-logic hierarchy alongside CPLDs and are typically chosen over ASICs when time-to-market, field upgradability, or low-to-medium volume production economics matter more than per-unit silicon cost. The APEX-20K family specifically pioneered the combination of LUT logic with embedded memory blocks called ESBs, predating modern system-on-chip FPGA architectures.
Key features of the EP20K200BC356-2 include 8,320 logic elements, 106,496 bits of embedded RAM, 277 user I/Os, and a 2.5 V core supply. The device is fabricated on a 0.22 µm CMOS process and supports a propagation delay of 2.5 ns at the -2 speed grade. The 356-LBGA package is a 35 mm × 35 mm fine-pitch ball grid array suitable for high-density board layouts.
Architecturally, APEX-20K devices use a four-level hierarchy of MegaLAB structures containing multiple Logic Array Blocks (LABs), each made up of ten Logic Elements (LEs). Embedded System Blocks (ESBs) provide dual-port RAM, ROM, or CAM functions, enabling true SOPC integration on a single PLD. This MultiCore architecture was novel at launch because it allowed designers to instantiate memory and logic without external SRAM or ROM chips.
Typical applications include telecommunications backplane glue logic, peripheral bus bridging (PCI, PCI-X, Utopia), high-speed data-path buffering, and legacy custom-compute or signal-processing prototyping where long-term supply stability matters. Designers typically pair the device with Intel/Altera MAX+PLUS II or Quartus for synthesis, place-and-route, and timing closure.
When designing with this part, note that the APEX-20K family is end-of-life; new designs should validate long-term supply through franchised distributors. The 2.5 V core supply requires careful decoupling and a multi-layer PCB to maintain signal integrity on the 277 I/Os.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes that are not compiled in the original Altera datasheet, helping engineers source and qualify the part quickly.
Drop-in alternatives for EP20K200BC356-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K200BC356-2 (same form factor and footprint) — differing in Process Technology, Operating Temperature, Package, Family, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K200BC356-2X
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K200BC356-2XV
✅ Drop-In✓ In Stock
$45 / Unit
View Datasheet →EP20K200BC356-1X
✅ Drop-In✓ In Stock
$285 / Unit
View Datasheet →EP20K200BC356-1
✅ Drop-In✓ In Stock
$335 / Unit
View Datasheet →EP20K100BC356-1
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K100EBC356-3N
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP20K200BC356-2 Maximum Ratings & Electrical Characteristics
| Series | APEX-20K |
| Device Family | APEX-20K (MultiCore PLD) |
| Logic Elements | 8,320 |
| Typical Gate Count | 200,000 gates |
| Embedded Memory | 106,496 bits |
| User I/Os | 277 |
| Logic Family | CMOS |
| Process Technology | 0.22 µm |
| Propagation Delay | 2.5 ns |
| Core Supply Voltage | 2.5 V |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Package | 356-LBGA (35 mm × 35 mm) |
| Speed Grade | -2 |
| Mounting Type | Surface Mount (BGA) |
| Maximum Frequency | 200 MHz |
EP20K200BC356-2 356-lbga (35 mm × 35 mm) Pin Configuration Guide
Pin configuration for EP20K200BC356-2 (356-lbga (35 mm × 35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K200BC356-2.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K200BC356-2 is suitable for 7 applications: Telecommunications Backplane Glue Logic, PCI / PCI-X Bridge and I/O Expansion, High-Speed Data-Path Buffering, Legacy Industrial Control Logic, Custom Compute / DSP Prototyping, Legacy Avionics and Defense Systems, Test & Measurement Instrumentation.
Telecommunications Backplane Glue Logic
The EP20K200BC356-2 fits telecom backplane bridging with its 8,320 logic elements and 277 user I/Os, enabling protocol conversion between SPI-4.2, UTOPIA, and PCI interfaces on a single chip. Its 106,496 bits of dual-port RAM allow packet buffering at line rates without external SRAM, while the 200 MHz internal frequency supports 100 MHz LVTTL/LVCMOS backplane operation. The 356-LBGA package keeps board area compact in dense line-card designs.
Recommended
PCI / PCI-X Bridge and I/O Expansion
With 277 user I/Os and embedded dual-port RAM, the EP20K200BC356-2 is well-suited for legacy PCI 32/33 and PCI-X bridge designs where a custom glue-logic ASIC would be uneconomical. The 2.5 ns propagation delay at speed grade -2 easily meets 66 MHz PCI timing, and the MultiCore architecture simplifies the integration of DMA engines, FIFOs, and register maps. Designers use MAX+PLUS II to instantiate PCI megafunctions and validate against PCI compliance checklists.
Recommended
High-Speed Data-Path Buffering
The 106,496 bits of dual-port embedded RAM make the EP20K200BC356-2 ideal for high-speed data-path buffering in serializer/deserializer (SERDES) companion logic, video pipelines, and digital signal processing front-ends. Each ESB (Embedded System Block) supports true dual-port operation, allowing simultaneous read/write at 200 MHz without external memory. The 277 I/Os provide ample width for parallel LVDS or LVTTL data buses between converter stages.
Recommended
Legacy Industrial Control Logic
Industrial control applications where long-term supply stability matters benefit from the EP20K200BC356-2's mature silicon and broad distributor stock. The 8,320 logic elements comfortably host multi-axis motion-control state machines, encoder interfaces, and deterministic real-time logic, while the 277 I/Os connect to opto-isolated digital I/O racks. Designers can lock firmware via the on-chip configuration memory and avoid external boot PROMs.
Recommended
Custom Compute / DSP Prototyping
Researchers and engineers prototyping custom compute or DSP accelerators use the EP20K200BC356-2 to validate algorithms before ASIC tape-out. The 8,320 logic elements support 16-bit × 16-bit multiplier-accumulator arrays and FIR filter structures at 200 MHz, while the embedded memory holds coefficient tables. Quartus II provides cycle-accurate simulation for verifying timing closure before committing to a custom silicon run.
Recommended
Legacy Avionics and Defense Systems
Long-lifecycle avionics and defense platforms where re-design is cost-prohibitive continue to use the EP20K200BC356-2 for mission-critical logic. The 356-LBGA package supports ruggedized conformal-coated PCB assemblies, and the MultiCore architecture's deterministic timing is valuable for safety-critical state machines. Stock allocation through franchised distributors ensures continued availability for sustainment programs.
Recommended
Test & Measurement Instrumentation
Test and measurement equipment leverages the EP20K200BC356-2's 277 I/Os to implement parallel capture logic, pattern generators, and protocol-analyzer state machines in a single FPGA. The 200 MHz maximum frequency and dual-port RAM allow real-time stimulus generation with deterministic timing. The 356-LBGA package fits standard instrumentation form factors while providing headroom for additional instrumentation channels.
Recommended
Recommended Products Summary
Engineering reference data for EP20K200BC356-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K200BC356-2X | EP20K200BC356-2XV | EP20K200BC356-1X | EP20K200BC356-1 | EP20K100BC356-1 | EP20K100EBC356-3N |
|---|---|---|---|---|---|---|---|
| Package | 356-LBGA | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 8,320 | 8,320 | 8,320 | 8,320 | 8,320 | 4,160 | 4,160 |
| Typical Gates | 200,000 | 200,000 | 200,000 | 200,000 | 200,000 | 100,000 | 100,000 |
| Speed Grade | -2 | -2 (extended temp) | -2 (extended temp + V tolerant) | -1 (slower) | -1 (slower) | -1 | -3 |
| Operating Temperature | 0 °C to +85 °C (commercial) | Extended temperature | Extended temperature | Extended temperature | Commercial | Commercial | Industrial (-40 to +85) |
| Core Supply Voltage | 2.5 V | 2.5 V | 2.5 V (voltage-tolerant I/O) | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest logic capacity in the APEX-20K 356-LBGA family (vs EP20K100BC356-1)
- Faster speed grade (-2) for higher system clock (vs EP20K200BC356-1)
- Commercial temperature grade (vs EP20K200BC356-2X)
Design Notes
The EP20K200BC356-2 requires a stable 2.5 V core rail and a separate 3.3 V (or 2.5 V) I/O bank supply. Estimated: based on typical APEX-20K ICCINT figures of ~500 mA at 200 MHz with all I/O switching, the device dissipates approximately 1.25 W at the core. Use a low-impedance power plane and 0.1 µF + 10 µF decoupling capacitor pairs near every supply pin to suppress switching noise.
The 356-LBGA package requires a multi-layer PCB with continuous ground and power planes under the device. Estimated: for a 1.0 mm pitch BGA, microvia or 0.4 mm via-in-pad technology is recommended to route signals out of the inner rows. Maintain 50 Ω controlled impedance on LVTTL/LVCMOS traces and use matched-length routing for clocks and DDR interfaces.
Do not confuse the EP20K200BC356-2 (200K gates, 8320 LE) with the EP20K100BC356 (100K gates, 4160 LE) when substituting in production; both share the same 356-LBGA footprint. The APEX-20K family is obsolete—validate long-term supply through franchised distributors before committing to new designs. Use Quartus II 13.0 SP1 or MAX+PLUS II as the final supported design environment.
Estimated: at 200 MHz and worst-case switching, the junction-to-ambient thermal resistance of the 356-LBGA is approximately 15-20 °C/W on a JEDEC 4-layer test board. Designers should provide at least 25 mm × 25 mm of unbroken copper plane under the package to keep junction temperature below 100 °C in commercial-grade applications. Forced-air cooling is recommended for sealed enclosures.
Compliance Information
RoHS/REACH compliance for EP20K200BC356-2 not explicitly stated in the verified web data; typical APEX-20K parts were launched before RoHS was mandatory and may require compliance verification at order time. Not AEC-Q100 qualified; not applicable for automotive use unless specifically screened.
