EP20K60EBC356-3 - 60K Gate APEX 20K FPGA, 356-BGA | Intel (Altera)
MPN: EP20K60EBC356-3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $86.4 | $864.00 |
| 100 | $78.2 | $7,820.00 |
| 500 | $71.5 | $35,750.00 |
| 1,000 | $65.8 | $65,800.00 |
EP20K60EBC356-3 Overview
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device that allows engineers to configure digital logic blocks, interconnect, and I/O behavior after manufacture. The APEX 20K family pioneered the MultiCore architecture, which integrates look-up tables (LUTs), embedded system blocks (ESBs) for memory and specialized functions, and a system-on-a-programmable-chip (SOPC) framework - effectively combining FPGA fabric with dedicated memory and I/O resources on a single die.
Key features of the EP20K60EBC356-3 include its 256 macro cells, 196 user I/Os, 160 MHz internal frequency, 1.72 ns propagation delay, and CMOS logic family implementation on a 0.22 um process. The 356-ball BGA (LBGA) package exposes both high-speed I/O banks and dedicated configuration/JTAG pins for in-system programmability via the Altera ByteBlaster or comparable download cables.
Architecturally, the APEX 20K family employs a hierarchical row/column interconnect fabric feeding LUT-based logic elements (LEs) and ESB blocks that can be configured as SRAM, ROM, or specialized logic such as CAM. The MultiCore architecture was an early example of heterogeneous FPGA fabric, allowing designers to instantiate large blocks of memory alongside gate-rich logic for DSP, glue logic, and bus-interface functions on the same silicon.
Typical applications for the EP20K60EBC356-3 include telecom line-card glue logic, industrial control and data acquisition front-ends, PCI/ISA bus bridging, and prototyping platforms for ASIC emulation. The device is also suitable for legacy systems that originally specified the APEX 20K family when it launched, including custom peripheral controllers and image-processing pipelines that fit within its 60K-gate capacity.
When designing with this part, confirm JTAG chain ordering and configuration mode (PS vs. AS, or JTAG) match your existing board layout, since the 356-BGA footprint leaves little room for rework. Engineers migrating to newer Intel Cyclone or MAX families should treat the EP20K60EBC356-3 as a long-term support component rather than a new design-in candidate.
This page synthesizes distributor pricing, same-brand drop-in alternatives from the APEX 20K family, and practical design notes not consolidated on any single manufacturer page.
Drop-in alternatives for EP20K60EBC356-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K60EBC356-3 (same form factor and footprint) β differing in Family, Operating Temperature, Package, Process Technology, Speed Grade.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP20K60EBC356-2
β Drop-Inβ In Stock
$98.75 / Unit
View Datasheet βEP20K60EBC356-3 Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Typical Gates | 60,000 |
| Logic Elements / Cells | 2,560 |
| Macro Cells | 256 |
| User I/Os | 196 |
| Logic Family | CMOS |
| Internal Frequency (max) | 160 MHz |
| Propagation Delay | 1.72 ns |
| Process Technology | 0.22 um |
| Core Supply Voltage | 1.8 V |
| Operating Temperature | 0C to +85C (Commercial) |
| Package | 356-LBGA (BGA-356) |
| Terminal Form | Ball |
| Package Shape | Square |
| Speed Grade | -3 (standard) |
| RoHS Status | Lead-free / RoHS Compliant |
| Architecture | MultiCore (LUT + ESB) |
| Configuration Method | JTAG / PS / AS (Altera download cable) |
EP20K60EBC356-3 Pin Configuration
| Pin A1 | I/O β User I/O (bank 1) |
| Pin A2 | I/O β User I/O (bank 1) |
| Pin B1 | VCCINT β 1.8 V core supply |
| Pin B2 | GND β Ground |
| Pin C1 | I/O β User I/O (bank 1) |
| Pin C2 | I/O β User I/O (bank 1) |
| Pin D1 | nCONFIG β Configuration control (active low) |
| Pin D2 | nSTATUS β Configuration status (active low) |
| Pin E1 | TDI β JTAG test data input |
| Pin E2 | TDO β JTAG test data output |
| Pin F1 | TCK β JTAG test clock |
| Pin F2 | TMS β JTAG test mode select |
Typical Applications
EP20K60EBC356-3 is suitable for 6 applications: Telecom Line-Card Glue Logic, Industrial Control and Data Acquisition, Legacy PCI/ISA Bus Bridging, ASIC Emulation and Prototyping, Image Processing Pipelines, Custom Peripheral Controllers.
Telecom Line-Card Glue Logic
The EP20K60EBC356-3's 60,000-gate capacity and 196 user I/Os make it well-suited for telecom line-card glue logic where it bridges backplane buses, implements protocol converters, and aggregates multiple low-speed serial streams. The 356-LBGA package supports the dense PCB layouts typical of multi-channel line cards, while the 1.72 ns propagation delay and 160 MHz internal frequency handle TDM bus arbitration and DS0/E1 framing. The MultiCore architecture's embedded system blocks (ESBs) provide on-chip FIFO memory for elastic buffering between clock domains, eliminating external SRAM in many glue-logic designs.
Recommended
Industrial Control and Data Acquisition
In industrial control systems, the EP20K60EBC356-3 implements custom motor-control state machines, ADC/DAC sequencing logic, and fieldbus protocol handlers such as Profibus or Modbus. Its 196 user I/Os accommodate multiple encoder inputs, PWM outputs, and isolated digital I/O channels without external muxing. The commercial 0C to 85C operating range suits cabinet-mounted industrial equipment, and the 1.8 V core with 3.3 V-tolerant I/O banks interfaces directly to legacy 5 V transceivers via level shifters.
Recommended
Legacy PCI/ISA Bus Bridging
The EP20K60EBC356-3 was widely deployed as a PCI-to-ISA bridge controller in industrial PCs and embedded SBCs of the early 2000s. Its 196 user I/Os handle 32-bit PCI bus signals plus address/data demultiplexing for ISA peripherals, while the MultiCore ESBs implement bus-master FIFOs and interrupt controllers in a single chip. The 160 MHz internal frequency exceeds the 33 MHz PCI clock requirement with comfortable timing margins, and the JTAG configuration chain simplifies in-system firmware updates across manufacturing lines.
Recommended
ASIC Emulation and Prototyping
ASIC designers used the EP20K60EBC356-3 as a multi-chip emulation platform for pre-silicon validation of custom ASICs in the 30K-60K gate range. Multiple devices are JTAG-chained to map large ASIC designs across a prototyping board, and the 356-LBGA package's high pin density preserves critical signal access. The Quartus II design flow supports partitioning, time-budgeting, and signal-trace features that simplify debug. While modern ASIC prototyping prefers Cyclone V or Stratix 10, the APEX 20K family remains in service for legacy validation flows.
Recommended
Image Processing Pipelines
The EP20K60EBC356-3's 2,560 logic elements and embedded system blocks suit medium-resolution image processing pipelines such as CCTV DVRs, machine-vision sensors, and medical imaging pre-processors. The ESBs implement line buffers and convolution kernels, while the LUT-based LEs handle pixel-wise arithmetic. The 196 user I/Os accommodate parallel camera interfaces (LVDS/TTL) and SDRAM connections for frame storage, and the 160 MHz internal frequency processes standard-definition video at full frame rates.
Recommended
Custom Peripheral Controllers
System designers deployed the EP20K60EBC356-3 as a custom peripheral controller in test equipment, point-of-sale terminals, and specialized printers where off-the-shelf microcontrollers lacked the parallel I/O bandwidth. Its 196 user I/Os interface to multiple peripheral buses simultaneously (parallel port, SCSI, custom keypad matrices), and the MultiCore ESBs implement DMA engines and scatter-gather descriptors. The 356-LBGA package fits compact embedded form factors, and JTAG programming supports field firmware updates via service ports.
Recommended
Recommended Products Summary
Engineering reference data for EP20K60EBC356-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K60EBC356-2 | EP20K60EBC356-2X | EP20K60EBC356-2N | EP20K60EBC356-1 | EP20K60EBC356-1X |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 356-LBGA | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same |
| Speed Grade | -3 (standard) | -2 (slower) | -2 (slower, extended) | -2 (slower, lead-free) | -1 (slowest) | -1 (slowest, extended) |
| Typical Gates | 60,000 | 60,000 | 60,000 | 60,000 | 60,000 | 60,000 |
| User I/Os | 196 | 196 | 196 | 196 | 196 | 196 |
| Internal Frequency (max) | 160 MHz | Approximately 120-140 MHz (estimated) | Approximately 120-140 MHz (estimated) | Approximately 120-140 MHz (estimated) | Approximately 100-120 MHz (estimated) | Approximately 100-120 MHz (estimated) |
| Propagation Delay | 1.72 ns | Approximately 2.0-2.2 ns (estimated) | Approximately 2.0-2.2 ns (estimated) | Approximately 2.0-2.2 ns (estimated) | Approximately 2.4-2.6 ns (estimated) | Approximately 2.4-2.6 ns (estimated) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster speed grade among APEX 20K 356-LBGA family (vs EP20K60EBC356-2)
- Standard timing bin vs. relaxed temperature processing (vs EP20K60EBC356-2X)
- Standard commercial temperature vs. lead-free processing (vs EP20K60EBC356-2N)
Design Notes
The 356-LBGA package requires a 1.0 mm or finer ball pitch PCB footprint with via-in-pad or dog-bone fanout. Use at least 4-layer stackup with continuous ground planes beneath the BGA to control impedance of the 160 MHz internal clock traces and reduce SSO (simultaneous switching output) noise. Decoupling: place 0.1 uF X7R ceramics on every VCCINT pin within 2 mm trace length, plus bulk 10 uF tantalum near the BGA.
At typical 60K-gate utilization running near 160 MHz internal frequency, the APEX 20K device dissipates approximately 1.5-2.5 W. The 356-LBGA package has a theta_JA of approximately 15-20 C/W with standard JEDEC test board, so junction temperature rise is 30-50C above ambient at full activity. For enclosed industrial enclosures, ensure at least 100 LFM airflow or mount the BGA on a PCB with a thermal via array connecting to inner copper planes.
Do not assume a speed-grade swap from -3 to -2 or -1 is always safe. Internal timing constraints (clock-to-out, setup/hold) relax by approximately 15-25% per speed step, but IOE (I/O element) timing scales differently. Re-run the Quartus II TimeQuest timing analyzer after any speed-grade substitution. Also verify JTAG chain order if multiple FPGAs share the bus - the EP20K60EBC356-3's TDI/TDO routing must match the BSDL file order.
The 196 user I/Os support LVTTL, LVCMOS, PCI, and SSTL standards when properly bank-configured. Place series termination resistors (22-33 ohm) on clock outputs and high-speed LVDS pairs. SSO analysis is required when more than 16 outputs switch simultaneously in a bank - use Quartus II's SSO calculator to validate against the APEX 20K IBIS model. Keep differential pair trace lengths matched within 150 mil for signals above 100 MHz.
Compliance Information
RoHS compliant per micro-semiconductor.com listing. Lead-free termination confirmed. REACH, halogen-free, and conflict minerals status not explicitly stated in verified web data - set to 'unknown' rather than fabricating compliance.
