EP20K400FI672-3 - APEX 20K 400K-Gate FPGA, 672-BGA | Altera
MPN: EP20K400FI672-3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $240 | $24,000.00 |
| 500 | $215 | $107,500.00 |
| 1,000 | $195 | $195,000.00 |
EP20K400FI672-3 Overview
An FPGA (Field Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated I/O cells that engineers can program after manufacture to implement arbitrary digital logic. Within the broader taxonomy, FPGAs sit between fixed-function ASICs and CPLDs, occupying a role where high logic density, parallel processing, and in-system reprogrammability are required. The APEX 20K series specifically combines logic elements with embedded memory blocks, allowing single-chip implementation of complex glue logic, datapath, and buffering functions.
Key specifications of the EP20K400FI672-3 include a nominal 2.5 V core supply (operating range 2.375 V to 2.625 V), 16640 logic elements, 212992 bits of embedded RAM, and 502 maximum user I/Os. The device is built on a CMOS process with 0.18 µm (or finer) technology, and supports in-system programmability via the IEEE 1149.1 JTAG boundary-scan interface and Altera's proprietary configuration scheme. The -3 speed grade trades slightly slower timing margins for lower cost compared to -2 and -1 grades.
Typical applications for the EP20K400FI672-3 span telecommunications line cards, industrial control backplanes, networking bridges, and legacy PCI/PCI-X bus controllers where the APEX 20K architecture remains deployed. Its high I/O count (502) and generous memory resources make it especially suited for parallel bus aggregation and protocol bridging.
When designing with this FPGA, ensure that the power supply sequencing matches Altera's APEX 20K reference design and that all I/O banks receive proper VCCIO voltages before driving outputs. Decoupling capacitors must be placed close to each power pin. JTAG configuration programming requires the Altera ByteBlaster or compatible download cable.
This page synthesizes distributor pricing, drop-in alternatives from the same APEX 20K family, and practical design notes not found in the standard manufacturer datasheet. All pricing is referenced as of 2026-09-08.
Drop-in alternatives for EP20K400FI672-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-3 (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, Process Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FI672-2
✅ Drop-In✓ In Stock
$92.4 / Unit
View Datasheet →EP20K400FI672-3V
✅ Drop-In✓ In Stock
$285 / Unit
View Datasheet →EP20K400FI672-3X
✅ Drop-In✓ In Stock
$142 / Unit
View Datasheet →EP20K400FI672-1
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP20K400FI672-2V
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400FC672-3
✅ Drop-In✓ In Stock
$138 / Unit
View Datasheet →EP20K400FI672-3 Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Series | EP20K400 |
| Logic Elements | 16640 |
| Total Gates | up to 400000 |
| Embedded RAM | 212992 bits |
| Maximum User I/O | 502 |
| Dedicated Inputs | 6 |
| Propagation Delay | 3.6 ns |
| Maximum Clock Frequency | 833 MHz |
| Supply Voltage (Nominal) | 2.5 V |
| Supply Voltage Range | 2.375 V to 2.625 V |
| Process Technology | CMOS |
| Package Type | PBGA (Plastic BGA) |
| Package Code | S-PBGA-B672 |
| Terminal Count | 672 |
| Terminal Pitch | 1.000 mm |
| Package Shape | Square BGA |
| Mounting Type | Surface Mount |
| Configuration Interface | JTAG (IEEE 1149.1) |
| MSL Level | 3 |
| Peak Reflow Temperature | 220 C |
EP20K400FI672-3 square bga Pin Configuration Guide
Pin configuration for EP20K400FI672-3 (square bga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-3.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-3 is suitable for 6 applications: Telecommunications Line Cards, Industrial Control Backplanes, Legacy PCI / PCI-X Bus Controllers, Networking Bridge and Router Line Cards, Test and Measurement Instrumentation, Medical Imaging Data Acquisition.
Telecommunications Line Cards
The EP20K400FI672-3's 502 user I/Os and 16640 logic elements make it well suited for legacy telecommunications line cards that aggregate T1/E1, ISDN, or low-speed serial links. Its 2.5 V core and 833 MHz clock rate handle protocol bridging, framing, and buffer management in central-office equipment. The 212992-bit embedded RAM provides on-chip packet buffering without external SRAM, reducing board complexity. For modern designs, Intel's Cyclone IV family replaces this role, but APEX 20K remains in service equipment.
Recommended
Industrial Control Backplanes
With 502 I/O lines and embedded RAM, the EP20K400FI672-3 integrates glue logic, encoder/decoder blocks, and protocol state machines for industrial backplanes such as VME, ISA, or proprietary field-bus aggregation. Its industrial-grade (F) temperature suffix suits factory-floor deployment. The 672-ball PBGA provides robust mechanical and thermal performance for backplane cards. Use the JTAG boundary-scan to verify backplane interconnect continuity during manufacturing test.
Recommended
Legacy PCI / PCI-X Bus Controllers
The EP20K400FI672-3 implements 32-bit/64-bit PCI and PCI-X bus controllers with up to 66 MHz operation, taking advantage of its high I/O count and 16640 LEs. Its 2.5 V core plus 3.3 V-tolerant I/O banks handle PCI signaling natively. Embedded RAM serves as DMA buffer or configuration space. Designers maintain long-life spare-part stock of the -3 grade for legacy server/storage upgrades.
Recommended
Networking Bridge and Router Line Cards
Bridge and router line cards of the APEX 20K era used the EP20K400FI672-3 to implement MAC controllers, table lookup engines, and forwarding logic at wire rate. Its 502 I/Os accommodate multiple Ethernet or SONET framer connections, while 212992-bit RAM holds routing tables and packet descriptors. The 833 MHz clock rate sustains gigabit forwarding at typical 64-byte minimum packet sizes on a per-port basis.
Recommended
Test and Measurement Instrumentation
The EP20K400FI672-3's 502 user I/Os and configurable logic make it ideal for digitizer cards, logic-analyzer probe multiplexers, and pattern-generator front-ends. Its embedded RAM stores captured waveforms while the 833 MHz logic rate enables real-time pattern synthesis at low MHz rates with deep sequencing. Industrial temperature grading suits lab and field-deployed instruments.
Recommended
Medical Imaging Data Acquisition
In medical imaging systems such as ultrasound front-ends and MRI digitizer boards, the EP20K400FI672-3 aggregates parallel ADC data streams and performs front-end DSP preprocessing. The 502 I/Os connect to multi-channel ADC banks, while 16640 LEs implement FIR filters and beamforming logic. The 212992-bit RAM holds line-buffer memory for image reconstruction pipelines.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FI672-2 | EP20K400FI672-3V | EP20K400FI672-3X | EP20K400FI672-1 | EP20K400FI672-2V | EP20K400FC672-3 |
|---|---|---|---|---|---|---|---|
| Package | 672-ball PBGA (S-PBGA-B672) | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same |
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Family | APEX 20K | APEX 20K - same | APEX 20K - same | APEX 20K - same | APEX 20K - same | APEX 20K - same | APEX 20K - same |
| Logic Elements | 16640 | 16640 - same | 16640 - same | 16640 - same | 16640 - same | 16640 - same | 16640 - same |
| Embedded RAM | 212992 bits | 212992 bits - same | 212992 bits - same | 212992 bits - same | 212992 bits - same | 212992 bits - same | 212992 bits - same |
| Maximum User I/O | 502 | 502 - same | 502 - same | 502 - same | 502 - same | 502 - same | 502 - same |
| Speed Grade | -3 (slowest, lowest cost) | -2 (medium) | -3 (same) | -3 (same) | -1 (fastest) | -2 (medium) | -3 (same) |
| Operating Temperature | Industrial (F-suffix) | Industrial (F) | Industrial (F) | Industrial (F) extended | Industrial (F) | Industrial (F) | Commercial (C) |
Key Differentiators
- Highest logic capacity in APEX 20K 672-ball BGA family (vs EP20K200FI484 series)
- Speed grade -3 offers lowest-cost entry to 400K-gate class (vs EP20K400FI672-1)
- Industrial temperature grading with 502 I/O count (vs EP20K400FC672-3 (commercial-temp variant))
Design Notes
Power sequencing is critical for the APEX 20K family. VCCINT (2.5 V core) must ramp before VCCIO (1.8 V/2.5 V/3.3 V I/O banks) per Altera's APEX 20K datasheet power-on-chip requirements. Reverse sequencing or simultaneous ramp can cause permanent latch-up. Use a supervisor IC (e.g., TPS3808) to enforce monotonic ramp and a minimum 100 µs delay between rails.
Estimated: the 672-ball PBGA has theta_JA of approximately 18 C/W with 4-layer JEDEC test board. At 2.5 V core, 100 MHz internal clock, and 80% logic utilization, typical power dissipation is 1.5-2.5 W, yielding 27-45 C junction rise above ambient. Add thermal vias beneath the BGA land pattern and copper pours on inner layers to reduce effective theta_JA to ~10-12 C/W for high-utilization designs.
BGA breakout routing requires microvia or via-in-pad technology to escape the 1.000 mm pitch ball grid. Place decoupling capacitors on the opposite PCB side directly beneath BGA balls using 0201 or 0402 footprints. Altera's APEX 20K datasheet recommends one 0.1 µF ceramic per VCCINT ball and one 0.01 µF per VCCIO ball for high-frequency noise suppression.
Do not assume JTAG chain integrity without a boundary-scan test - APEX 20K devices in 672-ball PBGA occasionally have hidden shorts between adjacent balls during reflow if paste volume is inconsistent. The MSL-3 rating mandates pre-bake at 125 C for at least 24 hours before assembly if the floor-life has been exceeded. Use X-ray inspection post-reflow on first-article boards.
Compliance Information
APEX 20K family predates RoHS mandates; compliance status not verified in current data. Not AEC-Q100 qualified - this is a commercial/industrial-grade FPGA.
