EP2AGX190FF35I5N - Arria II GX FPGA 181K LE FC-FBGA-1152 | Intel
MPN: EP2AGX190FF35I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2109.78 | $2,109.78 |
| 10 | $1999.5 | $19,995.00 |
| 100 | $1850 | $185,000.00 |
| 500 | $1720 | $860,000.00 |
| 1,000 | $1605 | $1,605,000.00 |
EP2AGX190FF35I5N Overview
A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnects, and embedded hardened IP such as transceivers, block RAM, and DSP blocks. FPGAs sit hierarchically between general-purpose microcontrollers and fixed-function ASICs: they offer parallel processing, deterministic latency, and the ability to be re-programmed in-system for evolving protocols or standards. The Arria II GX family targets the mid-range transceiver market, providing multi-gigabit serial capability without the cost or power of higher-end Stratix devices.
Key differentiating features of the EP2AGX190FF35I5N include up to 16 integrated transceivers supporting data rates to 3.75 Gbps (CPRI/OBSAI, PCIe Gen1, SATA, XAUI), dedicated hard memory controllers, up to 8 PLLs, and per-channel dynamic reconfiguration of PHY parameters. The 40 nm process enables substantial logic density at substantially lower static power than the prior 65 nm Stratix IV generation. Embedded PCI Express Gen1 hard IP blocks offload the protocol layer from user logic, freeing fabric for application processing.
The architecture combines a rich fabric of adaptive logic modules (ALMs), M20K block RAMs, and DSP blocks supporting 18x18 multipliers. The transceiver PMA layer features adaptive equalization and output pre-emphasis, while the PCS layer implements 8b/10b, word alignment, and rate-matching logic. Multi-rail power sequencing is handled by an on-chip Voltage Sensing circuitry that cooperates with external regulators.
Typical applications include wireless baseband processing (CPRI/OBSAI links between radio units and baseband cards), high-definition video broadcast infrastructure, defense and avionics signal processing, medical imaging pipelines, and industrial control planes requiring deterministic parallel DSP. Designers choose Arria II GX where Stratix IV is over-spec and Cyclone IV is under-spec.
When designing with this device, ensure your PCB supports 1152-ball FC-FBGA fine-pitch BGA routing with microvia stacks, allocate sufficient PCB layers (typically 12+), and validate power-rail sequencing against the in-system update requirements. Use the Quartus II 64-bit toolchain for synthesis, place-and-route, and timing closure.
This page synthesizes distributor pricing, drop-in alternatives drawn from the same Altera/Intel Arria II GX family, and practical design notes not collected in the manufacturer datasheet, providing engineers with a single decision-ready reference.
Drop-in alternatives for EP2AGX190FF35I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX190FF35I5N (same form factor and footprint) — differing in Package, Mounting Type, RoHS Status, Operating Temperature, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGX190FF35I5G
✅ Drop-In✓ In Stock
$1350 / Unit
View Datasheet →EP2AGX190FF35I3N
✅ Drop-In✓ In Stock
$1190 / Unit
View Datasheet →EP2AGX190FF35I3G
✅ Drop-In✓ In Stock
$1840 / Unit
View Datasheet →EP2AGX190FF35C5G
✅ Drop-In✓ In Stock
$1245 / Unit
View Datasheet →EP2AGX190FF35C4G
✅ Drop-In✓ In Stock
$2350 / Unit
View Datasheet →EP2AGX190FF35I5N Maximum Ratings & Electrical Characteristics
| Device Family | Arria II GX |
| Logic Elements | 181165 |
| Adaptive Logic Modules (ALMs) | 7612 |
| User I/Os | 612 |
| Embedded Memory (Kbits) | 10177.536 |
| Number of Transceivers | Up to 16 |
| Transceiver Data Rate | Up to 3.75 Gbps |
| Core Supply Voltage | 0.9 V |
| Process Technology | 40 nm |
| Package Type | 1152-ball FC-FBGA (FF35) |
| Operating Temperature | -40C to +100C (Industrial) |
| Hard Memory Controllers | Yes |
| Hard PCI Express Blocks | Yes (Gen1) |
| PLLs | Up to 8 |
| RoHS Status | Compliant |
EP2AGX190FF35I5N 1152-ball fc-fbga (ff35) Pin Configuration Guide
Pin configuration for EP2AGX190FF35I5N (1152-ball fc-fbga (ff35) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX190FF35I5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX190FF35I5N is suitable for 6 applications: Wireless Baseband / CPRI Backhaul, High-Definition Video Broadcast Infrastructure, Defense and Avionics Signal Processing, Medical Imaging Pipelines, Industrial Test and Measurement, Telecom Datacenter Line Cards.
Wireless Baseband / CPRI Backhaul
The EP2AGX190FF35I5N is widely used in wireless baseband processing cards that interface with remote radio heads via the Common Public Radio Interface (CPRI) or OBSAI protocol. Its 16 multi-gigabit transceivers operating up to 3.75 Gbps comfortably support CPRI line rates from 614.4 Mbps to 3.072 Gbps across multiple sectors without external PHY devices. The 181K logic elements and 9.5 Mbits of block RAM allow baseband channel cards to perform antenna signal processing, FFT/IFFT computation, and digital predistortion simultaneously. Compared with ASICs, the FPGA enables rapid adoption of evolving LTE and 5G NR protocols in development and small-cell deployments.
Recommended
High-Definition Video Broadcast Infrastructure
Broadcast studios and contribution links rely on the EP2AGX190FF35I5N for SDI/HD-SDI/3G-SDI aggregation, format conversion, and light video processing. The 612 user I/Os allow simultaneous handling of dozens of SDI streams alongside genlock, audio embedders, and ancillary data channels. The transceiver lanes support SMPTE 2022-6/2110 IP-based video transport or compressed MPEG-TS distribution, replacing separate serializer/deserializer chips. Designers exploit the FPGA's parallel DSP blocks for de-interlacing, scaling, and watermarking in real time at sub-frame latency, which is critical for live broadcast workflows.
Recommended
Defense and Avionics Signal Processing
Military and aerospace platforms adopt the EP2AGX190FF35I5N for radar, electronic warfare, and secure communications subsystems. Its industrial temperature grade (-40C to +100C) and 40 nm process technology give predictable performance in harsh thermal environments, while the 1152-ball FC-FBGA package meets shock and vibration profiles when properly underfilled. The hardened PCI Express Gen1 endpoints and DDR3 memory controllers simplify integration with ruggedized compute sleds. Defense programs benefit from the FPGA's ability to absorb late-stage waveform changes, anti-jamming updates, and mission-specific encryption kernels without respin.
Recommended
Medical Imaging Pipelines
The EP2AGX190FF35I5N supports real-time image processing in MRI, CT, ultrasound, and digital X-ray systems where deterministic latency is required. The device's parallel DSP blocks accelerate filter kernels, beamformers, and back-projection algorithms, while 9.5 Mbits of block RAM hold line buffers and lookup tables for FBP and iterative reconstruction. Low static power dissipation reduces heat load inside the scanner bore, contributing to patient comfort and system reliability. Designers use the FPGA to pre-process raw sensor data before handing clean frames to the host CPU for clinical reconstruction and review.
Recommended
Industrial Test and Measurement
Benchtop and rack-mount T&M equipment use the EP2AGX190FF35I5N for arbitrary waveform generation, mixed-signal acquisition, and protocol-aware triggering. The 16 multi-gigabit transceivers handle USB 3.0, SATA, and proprietary high-speed serial probes, while 612 LVDS-capable I/Os interface with parallel ADCs and DACs at hundreds of MSPS. The large logic capacity allows real-time FFT, decimation, and PRBS error counters to run alongside GUI logic. Industrial customers appreciate the FPGA's ability to be re-configured for new standards (LPDDR4, PCIe Gen2 later) without board redesign.
Recommended
Telecom Datacenter Line Cards
Datacenter top-of-rack switches and edge telecom line cards leverage the EP2AGX190FF35I5N for high-density packet processing and traffic management. The 16 transceivers can be split across multiple QSFP+ front-panel ports carrying 10 GbE or 4x2.5G aggregation links, while 612 user I/Os expose control plane signals to switch fabric ASICs. The on-chip DDR3 memory controller and embedded packet classification engines minimize external memory pressure. Compared with merchant silicon, the FPGA approach supports proprietary encapsulation, encryption, and timing protocols for telecom operators.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX190FF35I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX190FF35I5G | EP2AGX190FF35I3N | EP2AGX190FF35I3G | EP2AGX190FF35C5G | EP2AGX190FF35C4G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FC-FBGA (FF35) | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same |
| Logic Elements | 181165 | 181165 | 181165 | 181165 | 181165 | 181165 |
| User I/Os | 612 | 612 | 612 | 612 | 612 | 612 |
| Speed Grade | -5 (slower) | -5 | -3 (faster) | -3 (faster) | -5 | -4 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Industrial | Commercial (0C to +85C) | Commercial (0C to +85C) |
| RoHS / Green | Pb-free (N suffix) | Green / RoHS-6 (G) | Pb-free (N) | Green / RoHS-6 (G) | Green / RoHS-6 (G) | Green / RoHS-6 (G) |
| Transceiver Count | Up to 16 | Up to 16 | Up to 16 | Up to 16 | Up to 16 | Up to 16 |
Key Differentiators
- Highest transceiver count in the Arria II GX family (vs EP2AGX125EF35I5G)
- Largest logic capacity in the FF35 package family (vs EP2AGX125EF35I5G)
- Industrial temperature grade suitable for harsh environments (vs EP2AGX190FF35C5G)
Design Notes
The 1152-ball FC-FBGA FF35 package requires a high-density PCB stack-up with microvia (laser-drilled) vias and 12 or more routing layers. Per Altera FC-BGA layout guidelines, designers should target 0.8 mm or 1.0 mm ball pitch, controlled-impedance 50-ohm single-ended / 100-ohm differential traces, and a solid thermal pad array beneath the package. Use HDI (High-Density Interconnect) via structures to break out from the inner rows. Simulate channel loss with the Hspice IBIS-AMI models from Altera before committing to stack-up.
Provide at least 3-4 independent supply rails: 0.9 V core (VCC), 1.1 V/1.2 V transceiver (VCCT), 2.5 V/3.3 V I/O (VCCIO), and a dedicated PLL analog supply (VCCA_PLL). Sequence core before transceivers per Altera power-up sequencing requirements. Use a dedicated Power Management Unit (e.g., LM26480, LTM4641, or equivalent) with soft-start and voltage-tracking. Decouple each rail with a combination of bulk, mid-frequency ceramic, and high-frequency MLCC capacitors placed within 100 mil of the balls.
Despite being on the 40 nm node, the EP2AGX190FF35I5N at full utilization (16 active transceivers + 80% logic + 9 Mbits BRAM) can dissipate 8-12 W. The FC-FBGA FF35 package thermal pad must be soldered to a 6 x 6 thermal via array (0.3 mm drilled, 0.5 mm pitched) connecting to a copper inner-plane heat-spreader. At industrial temperature grade, derate Tj below 100C. Use thermal simulation (FloTHERM or ICEPAK) during PCB layout to validate junction temperature under worst-case airflow.
Do not rely on default Quartus II pin assignments without reviewing the FF35 pinout file for bank-VCCIO compatibility. Mixing 1.5 V and 1.8 V on the same I/O bank causes permanent damage. Confirm transceiver reference clock source impedance and AC-coupling capacitor selection against the Arria II GX Transceiver User Guide section on external reference clock circuitry. When migrating between speed grades (-5 to -3), re-validate timing closure because the placement and routing differ.
Compliance Information
RoHS and REACH compliant per manufacturer part marking (Pb-free N suffix). Industrial temperature grade does not satisfy AEC-Q100 (automotive grade); not AEC-Q100 qualified. Halogen-free status not explicitly stated in distributor data - check latest Intel material declaration before committing for halogen-sensitive applications.
