EP2AGZ350FH29C4G - Arria II GZ FPGA 350K LE FBGA-780 | Intel
MPN: EP2AGZ350FH29C4G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2845 | $2,845.00 |
| 10 | $2680 | $26,800.00 |
| 100 | $2520 | $252,000.00 |
| 500 | $2360 | $1,180,000.00 |
| 1,000 | $2205 | $2,205,000.00 |
EP2AGZ350FH29C4G Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device that combines configurable logic blocks, programmable interconnect, and dedicated hard IP such as transceivers, multipliers, and block RAM. FPGAs occupy the hierarchy: FPGA -> programmable logic -> digital IC -> integrated circuit -> semiconductor. Arria II GZ FPGAs specifically target applications that need 8.5-Gbps transceivers and substantial DSP resources without the cost of Stratix-class silicon.
Key features of the EP2AGZ350FH29C4G include 350K logic elements (LEs), 18,424 Kbits of M20K block RAM plus 1,425 Kbits of MLAB, sixteen 8.5-Gbps transceivers supporting PCI Express Gen2 and Gigabit Ethernet, 1,152 embedded multipliers (18x18), and up to 552 user I/O pins. The FH29 780-ball flip-chip BGA package supports high-speed signal integrity and a wide operating temperature range.
Typical applications include high-performance digital signal processing, software-defined radio (SDR), video processing and broadcast infrastructure, ASIC prototyping, and high-speed serial connectivity in telecommunications, defense, and test-and-measurement systems. The C4 speed grade and -4 transceiver grade position the part for cost-optimized commercial applications; -I (industrial) and -I5/I6 grades exist for harsher environments.
When designing with this device, ensure proper PCB layout with matched-length traces for high-speed transceivers, adequate power-rail decoupling, and thermal management via the package's exposed thermal array. Configure the FPGA using Intel Quartus II design software (or the Quartus Prime Lite edition for cost-free development).
Drop-in alternatives for EP2AGZ350FH29C4G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FH29C4G (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature, Mounting Type, RoHS Status.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGZ350FH29C3N
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View Datasheet βEP2AGZ350FH29C3G
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View Datasheet βEP2AGZ300FH29C4N
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View Datasheet βEP2AGZ300FH29C4G
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View Datasheet βEP2AGZ350FH29C4G Maximum Ratings & Electrical Characteristics
| Family | Arria II GZ |
| Logic Elements (LEs) | 350,000 |
| M20K Block RAM (bits) | 18,424 Kbits |
| MLAB Memory (bits) | 1,425 Kbits |
| Embedded Multipliers (18x18) | 1,152 |
| Transceivers | 16 (8.5 Gbps) |
| Maximum User I/O | 552 |
| Package | 780-ball Flip-Chip BGA (FH29) |
| Process Node | 40 nm |
| Speed Grade | C4 |
| Operating Temperature | 0C to +85C (Commercial) |
| Transceiver Grade | -4 |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
EP2AGZ350FH29C4G 780-ball flip-chip bga (fh29) Pin Configuration Guide
Pin configuration for EP2AGZ350FH29C4G (780-ball flip-chip bga (fh29) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FH29C4G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FH29C4G is suitable for 7 applications: High-Performance Digital Signal Processing, Software-Defined Radio (SDR) Baseband, Video Processing and Broadcast Infrastructure, ASIC Prototyping and Emulation, Telecommunications Backhaul and Fronthaul, Test and Measurement Instrumentation, Aerospace and Defense Signal Processing.
High-Performance Digital Signal Processing
The EP2AGZ350FH29C4G's 1,152 embedded 18x18 multipliers and 350K logic elements make it well suited for high-performance DSP applications such as real-time FFT, FIR filtering, and digital up/down conversion. The M20K block RAM (18,424 Kbits) provides the memory bandwidth required for parallel data-path DSP pipelines, with each M20K block capable of running at up to 600 MHz. In a typical radar or SDR processing chain, the device sustains multi-Gsample/s processing rates while leaving headroom for system glue logic. Quartus II's DSP Builder tool integrates with MathWorks MATLAB/Simulink for floating-point model deployment, allowing rapid prototyping of DSP kernels directly onto the FPGA fabric. The 8.5-Gbps transceivers aggregate processed data for transmission to host processors or backplane interconnect.
Recommended
Software-Defined Radio (SDR) Baseband
With 16 transceivers operating at 8.5 Gbps and a 350K-LE capacity, the EP2AGZ350FH29C4G serves as a powerful baseband processor in software-defined radio platforms spanning cellular, public-safety, and military waveforms. The transceiver bandwidth enables multi-band RF sampling and direct conversion to baseband from antennas operating up to several GHz. The DSP multiplier count supports wideband channelization, digital upconversion (DUC), and digital downconversion (DDC) for waveforms such as LTE, WiMAX, and proprietary tactical radios. Designers benefit from the Altera/Intel DSP IP cores, which accelerate FFT/IFFT, Viterbi, and Turbo decoding. The FH29 780-ball BGA supplies ample high-speed I/O for digitizer interfaces such as JESD204B to companion ADCs.
Recommended
Video Processing and Broadcast Infrastructure
The EP2AGZ350FH29C4G handles real-time processing of uncompressed video streams including 4K/UHD workflows in broadcast and production environments. Its high block-RAM bandwidth (up to 22.4 Tbps) supports multi-frame buffering, color-space conversion, scaling, and de-interlacing pipelines with minimal external memory. The 8.5-Gbps transceivers interface directly to SMPTE 2022-6, SMPTE 2110, and 12G-SDI coaxial interfaces through appropriate PHYs. Broadcast applications benefit from FPGA deterministic latency critical for live production switching. The C4 speed grade supports typical broadcast timing budgets at commercial operating temperatures. Quartus II provides broadcast-specific IP cores including SDI, HDMI, and DisplayPort interface blocks.
Recommended
ASIC Prototyping and Emulation
ASIC design teams use the EP2AGZ350FH29C4G to prototype multi-million-gate ASICs before tape-out, leveraging its 350K logic elements plus embedded multipliers and block RAM to map complex SoC designs. The Quartus II design software supports industrial-standard HDL entry (VHDL/Verilog/SystemVerilog) and integrates with commercial ASIC prototyping flows such as Synopsys Certify and Mentor Seamless. Multi-FPGA partitioning tools split large ASIC designs across multiple Arria II GZ boards interconnected via high-speed serial links. The 8.5-Gbps transceivers enable gigabit-level bandwidth between FPGAs in multi-chip emulation systems. The C4 speed grade provides predictable timing margin during ASIC design verification.
Recommended
Telecommunications Backhaul and Fronthaul
Telecommunications infrastructure including CPRI, OBSAI, and Ethernet backhaul/fronthaul networks deploy the EP2AGZ350FH29C4G for protocol conversion, packet processing, and aggregation. The 8.5-Gbps transceivers support CPRI rates up to option 6 (4.9152 Gbps) with margin, and multiple transceivers enable aggregation of several RRH (Remote Radio Head) streams. The high logic count supports IPsec/MACsec encryption and quality-of-service policy enforcement. FPGA-based fronthaul equipment accelerates time-to-market for new radio access technologies such as 5G NR. Commercial temperature-grade operation fits central-office deployments with controlled environments.
Recommended
Test and Measurement Instrumentation
High-end test-and-measurement instruments such as logic analyzers, protocol analyzers, and arbitrary waveform generators leverage the EP2AGZ350FH29C4G's high logic density, abundant block RAM, and 8.5-Gbps transceiver bandwidth for multi-channel acquisition and generation. Each instrument channel can be assigned to a dedicated transceiver, allowing real-time correlation across multiple signal lanes for protocols such as PCIe, USB 3.0, SATA, and multi-lane Ethernet. The block RAM serves as deep capture buffer for protocol violation analysis. The Quartus II development environment enables rapid customization of protocol-specific decoders and triggers. Commercial C4 speed grade operation fits laboratory ambient conditions.
Recommended
Aerospace and Defense Signal Processing
Defense applications including radar, electronic warfare (EW), and secure communications use the EP2AGZ350FH29C4G for wideband signal capture, channelized processing, and digital beamforming. With 1,152 multipliers and 350K LEs, the device sustains real-time processing of wideband RF data streams captured by high-speed ADCs through the 8.5-Gbps transceivers. Defense integrators favor the Altera/Intel FPGA toolchain for its support of standards such as VITA 49 (VITA Radio Transport) and OpenVPX. The FH29 BGA package withstands the vibration profiles of airborne platforms. C4 commercial grade suits ground-station and shipboard environments; -I industrial or MIL-spec variants are required for harsher airborne use.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FH29C4G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350FH29C3N | EP2AGZ350FH29C3G | EP2AGZ300FH29C4N | EP2AGZ300FH29C4G | EP2AGZ350FF35C4G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 780-ball Flip-Chip BGA (FH29) | 780-ball Flip-Chip BGA (FH29) | 780-ball Flip-Chip BGA (FH29) | 780-ball Flip-Chip BGA (FH29) | 780-ball Flip-Chip BGA (FH29) | 1152-ball Flip-Chip BGA (FF35) |
| Logic Elements (LEs) | 350,000 | 350,000 | 350,000 | 300,000 | 300,000 | 350,000 |
| Speed Grade | C4 | C3 | C3 | C4 | C4 | C4 |
| M20K Block RAM (Kbits) | 18,424 | 18,424 | 18,424 | 14,267 | 14,267 | 18,424 |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
Key Differentiators
- Highest-density member of the Arria II GZ family (vs EP2AGZ300FH29C4G)
- Optimized speed grade for cost-sensitive commercial applications (vs EP2AGZ350FH29C3G)
- 8.5-Gbps transceiver bandwidth outperforms the GX series (vs EP2AGX260EF29C5G)
Design Notes
Estimated: The Arria II GZ family in the FH29 780-ball flip-chip BGA can dissipate up to approximately 8-12 W depending on logic utilization and transceiver activity. The flip-chip BGA uses the die backside thermal interface; design a PCB thermal solution with thermal vias under the package thermal pad array. Reference the Arria II GZ device handbook PowerPlay section for typical and worst-case power estimation. Use the Quartus II Early Power Estimator before design completion to validate thermal headroom.
Design the FH29 780-ball BGA PCB footprint with 1.0 mm ball pitch and microvia stack-up. Use a 14-16 layer stack-up with dedicated transceiver reference planes. Matched-length routing of 8.5-Gbps transceiver lanes is critical - skew should be held below 5 ps for PCIe Gen2 compliance. DC blocking capacitors are required on every transceiver TX output; AC-coupling capacitor values (typically 100 nF) should be located within 0.5 inch of the device ball. See the Altera/Intel Arria II GZ PCB Design Guidelines chapter for detailed routing rules.
Power rail sequencing for the Arria II GZ requires the VCC and VCCPD rails to ramp together per datasheet specification. Use a power sequencer or coordinated LDO/DCDC outputs to prevent device latch-up. Decoupling: place 0402 ceramic capacitors every 5-8 mm along the FPGA power rails, with bulk decoupling (10-22 uF) at regulator outputs. Transceiver supply (VCCH_GXB) noise must remain below 10 mVpp for 8.5-Gbps link reliability.
Do not confuse the speed grade suffix C4 with C3 - the C4 grade provides tighter timing margins than C3 at higher cost. The 'G' suffix in the part number indicates lead-free / RoHS compliance. Pin assignment of unused transceiver channels should be terminated per the device handbook to avoid floating inputs. Configuration scheme selection (AS, PS, JTAG, FPP) affects both the configuration memory cost and configuration time; verify against your in-system update requirements.
Compliance Information
RoHS compliance indicated by 'G' suffix in MPN. AEC-Q100 not applicable for FPGAs (automotive qualification follows different standards). Lead-free per Altera/Intel product page.
