EP2AGZ350FF35C4G - 350K LE Arria II GZ FPGA 1152-FBGA | Intel
MPN: EP2AGZ350FF35C4G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1695 | $16,950.00 |
| 25 | $1620 | $40,500.00 |
| 100 | $1480 | $148,000.00 |
| 250 | $1395 | $348,750.00 |
EP2AGZ350FF35C4G Overview
What is an FPGA? A field-programmable gate array (FPGA) is a semiconductor device built around a matrix of configurable logic blocks (CLBs) connected via programmable interconnect. Unlike fixed-function ASICs, FPGAs can be reconfigured by the designer after manufacture, making them ideal for prototyping, low-volume production, and designs where standards evolve. Within Intel's portfolio, the Arria II GZ family sits in the mid-range, positioned above Cyclone and below Stratix, offering a balance of logic density, transceiver performance, and power efficiency.
Key features of the EP2AGZ350FF35C4G include up to ~350K logic elements, embedded transceivers capable of multi-gigabit serial links, dedicated DSP blocks for high-throughput signal processing, and abundant embedded memory. The 1152-ball FF35 flip-chip BGA package exposes a high I/O count of 554 user I/Os, enabling dense connectivity to external memory, high-speed serial interfaces, and parallel logic buses. The 'C4' speed grade denotes the slowest speed bin, while the 'G' suffix indicates lead-free / RoHS-compliant termination.
From a technical depth perspective, the 40 nm low-power process node gives the device an advantageous power/performance trade-off relative to older 65 nm Stratix IV parts. Its architecture is well-suited for protocols such as PCI Express Gen2, Serial RapidIO, Gigabit Ethernet, XAUI, and high-speed custom serial links where the embedded transceivers deliver low-jitter multi-gigabit operation. Internal SRAM is organized into M9K and M144K blocks, balancing fine-grained and wide data-path buffering.
Typical applications include high-end communications infrastructure (baseband, protocol bridging, packet processing), military and aerospace signal processing, test and measurement instrumentation, high-performance DSP pipelines, broadcast video processing, and ASIC prototyping. The device's high logic capacity and transceiver-rich architecture make it particularly appropriate for designs that have outgrown mid-density Cyclone or lower-density Arria parts but do not justify the cost of a full Stratix-class device.
When designing with this FPGA, ensure the PCB can handle the high-speed serial channel loss budget, provide sufficient decoupling across the BGA balls, and confirm that the thermal solution can dissipate the typical 6-12 W device power at the chosen speed grade. Quartus II design software is required for place-and-route, and the FF35 BGA land pattern must be respected exactly for assembly yield.
This page synthesizes distributor stock and pricing, same-family drop-in alternatives that share the FF35 footprint, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2AGZ350FF35C4G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FF35C4G (same form factor and footprint) — differing in Package, RoHS Status, Transceivers, Logic Elements, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGZ350FF35C3G
✅ Drop-In✓ In Stock
$2680 / Unit
View Datasheet →EP2AGZ350FF35C3N
✅ Drop-In✓ In Stock
$2250 / Unit
View Datasheet →EP2AGZ350FF35I4G
✅ Drop-In✓ In Stock
$5824.66 / Unit
View Datasheet →EP2AGZ300FF35C4G
✅ Drop-In✓ In Stock
$2240 / Unit
View Datasheet →EP2AGZ225FF35C4G
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2AGX260FF35C4G
✅ Drop-In✓ In Stock
$1420 / Unit
View Datasheet →EP2AGZ350FF35C4G Maximum Ratings & Electrical Characteristics
| Series | Arria II GZ |
| Family | Arria II GZ |
| Process Node | 40 nm |
| Package | 1152-ball FC-FBGA (FF35) |
| User I/Os | 554 |
| Speed Grade | C4 (slowest) |
| RoHS Status | Compliant (G suffix) |
| Mounting Type | Surface Mount (BGA) |
| Manufacturer | Intel (formerly Altera) |
EP2AGZ350FF35C4G 1152-ball fc-fbga (ff35) Pin Configuration Guide
Pin configuration for EP2AGZ350FF35C4G (1152-ball fc-fbga (ff35) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FF35C4G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FF35C4G is suitable for 6 applications: High-Speed Communications Backhaul, ASIC Prototyping, Test and Measurement Instrumentation, Broadcast Video Processing, Military and Aerospace Signal Processing, Industrial Automation and Machine Vision.
High-Speed Communications Backhaul
The EP2AGZ350FF35C4G fits high-speed communications backhaul because its embedded multi-gigabit transceivers and ~350K logic elements allow it to bridge CPRI/OBSAI links to Ethernet, while DSP blocks implement channel estimation and FEC. Placed on a line card with SFP+ cages and external DDR3 memory, it replaces several discrete bridging ASICs and adapts easily as standards evolve. The 1152-ball FF35 BGA exposes enough I/O for parallel side-band and management interfaces, and the GZ transceiver IP supports the typical 6.144 Gbps CPRI line rate without external PHY silicon.
Recommended
ASIC Prototyping
The EP2AGZ350FF35C4G is well suited to ASIC prototyping because ~350K LEs and the rich embedded memory hierarchy (M9K + M144K) can map large ASIC RTL partitions, and the abundant transceivers emulate high-speed ASIC SERDES for IO validation. Designers partition the ASIC netlist across one or more FF35 boards, using Quartus II TimeQuest sign-off to validate timing pre-tapeout. Compared with ASIC re-spins, a single FPGA prototype iteration is dramatically cheaper and the same FF35 package enables quick capacity swaps (Z225/Z300/Z350) during debug.
Recommended
Test and Measurement Instrumentation
The EP2AGZ350FF35C4G suits high-end test and measurement instruments because the multi-gigabit transceivers can stream ADC samples off-board at 5-6 Gbps, while ~350K LEs implement real-time DSP for FFTs, filters, and modulation analysis. Its abundant embedded memory buffers long acquisitions before host offload, and the FF35 BGA exposes parallel LVDS pairs to ADCs/DACs directly. Engineers value the in-system re-programmability for adding new measurement modes after deployment, which is impossible with fixed-function ASICS in the same price band.
Recommended
Broadcast Video Processing
The EP2AGZ350FF35C4G supports broadcast video processing applications such as multi-channel SD/HD/3G-SDI switching, color-space conversion, and frame-rate conversion. Its transceivers drive SMPTE-compliant SDI rates up to 3 Gbps directly, while DSP blocks implement scalers and deinterlacers in real time. The FF35 package provides ample user I/O for HDMI, DisplayPort, and parallel video buses, and the 40 nm GZ process is power-efficient enough for fan-cooled rackmount frames. Designers can reconfigure the device per product variant without re-spinning PCBs.
Recommended
Military and Aerospace Signal Processing
The EP2AGZ350FF35C4G (industrial-temp variants like EP2AGZ350FF35I4G) serves military and aerospace signal-processing applications including radar front-end preprocessing, software-defined radio baseband, and electronic-warfare jammers. Its transceivers support wideband IF sampling chains, and ~350K LEs implement pulse compression, beamforming weights, and adaptive filters in real time. Compared with rad-hard ASICs, the FPGA dramatically shortens iteration time while still meeting ruggedized MIL-spec board designs. Designers pair it with external ADC/DAC companion parts and rugged power conditioning.
Recommended
Industrial Automation and Machine Vision
The EP2AGZ350FF35C4G fits industrial automation and machine vision controllers where multi-camera CoaXPress or GigE Vision aggregation requires the embedded transceivers, and ~350K LEs run real-time image preprocessing, defect detection, and PLC logic in parallel. The 40 nm low-power process keeps thermal output manageable inside sealed IP67 enclosures with limited airflow. Reuse of the FF35 footprint lets designers scale across Z225/Z300/Z350 SKUs depending on line-scan resolution and frame rate, without changing the carrier PCB. Industrial-grade I4 temperature variants are available on the same footprint.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FF35C4G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350FF35C3G | EP2AGZ350FF35C3N | EP2AGZ350FF35I4G | EP2AGZ300FF35C4G | EP2AGZ225FF35C4G | EP2AGX260FF35C4G |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1152-ball FC-FBGA (FF35) | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same |
| Family / Die | Arria II GZ / Z350 | Arria II GZ / Z350 (same die) | Arria II GZ / Z350 (same die) | Arria II GZ / Z350 (same die) | Arria II GZ / Z300 (different die) | Arria II GZ / Z225 (different die) | Arria II GX / X260 (different family) |
| Approx. Logic Elements | ~350K | ~350K | ~350K | ~350K | ~300K | ~225K | ~260K (Arria II GX) |
| Speed Grade | C4 (slowest) | C3 (faster) | C3 (faster) | C4 (industrial temp) | C4 | C4 | C4 |
| Temperature Grade | Commercial | Commercial | Industrial | Industrial | Commercial | Commercial | Commercial |
| Embedded Transceivers | Yes (Arria II GZ multi-gigabit) | Yes (same GZ transceivers) | Yes (same GZ transceivers) | Yes (same GZ transceivers) | Yes (GZ transceivers) | Yes (GZ transceivers) | Yes (GX transceivers, fewer channels) |
| RoHS Compliance (G suffix) | Yes (G) | Yes (G) | No (N suffix, leaded) | Yes (G) | Yes (G) | Yes (G) | Yes (G) |
Key Differentiators
- Highest logic density in the Arria II GZ FF35 package family (vs EP2AGZ300FF35C4G)
- Drop-in speed upgrade without PCB rework (vs EP2AGZ350FF35C3G)
- Arria II GZ transceivers outperform the lower-cost Arria II GX (vs EP2AGX260FF35C4G)
Design Notes
Estimated: based on a typical Arria II GZ Z350 die core power of 6-12 W at the C4 speed grade and a FC-FBGA theta_JA of roughly 8-10 C/W (vendor-specific value needed), the device typically requires a heatspreader or heatsink for sustained commercial-temperature operation. Designers should include a thermal relief copper pour under the BGA thermal balls and confirm the cooling solution under worst-case utilization before committing to the layout.
The 1152-ball FF35 flip-chip BGA demands a high-density PCB build-up with microvias-in-pad and matched-length impedance control on all transceiver lanes. Use the manufacturer land-pattern file directly (do not redraw it) and keep decoupling within the BGA breakout area to minimize inductance on Vcore/Vio rails. Reference design PCB stack-up guidance for Arria II GZ is available in the family user guide and applies unchanged to the FF35 package.
All multi-gigabit transceiver channels require 85-100 ohm differential impedance and matched lane lengths within the tolerance given by the protocol IP (PCIe Gen2 typically <5 mil). Place AC-coupling capacitors on the transmit side of each serial link per the Intel pin connection guidelines, and avoid routing any noisy digital signals across the transceiver ball rows. Pre-emphasis and equalization settings should be tuned with the Intel Transceiver Toolkit against the actual PCB.
Do not assume a single Quartus II version supports both Arria II GZ and the latest Intel FPGA devices - the C4 speed grade may be missing from newer Quartus Prime releases, so designers should pin Quartus II 13.0 or another verified version. Also confirm the G suffix indicates lead-free/RoHS (the N suffix is leaded and may not be acceptable for some end markets), and verify the JTAG chain including any companion configuration devices on the board before taping out the PCB.
Compliance Information
G suffix in the order code denotes lead-free / RoHS-compliant termination. AEC-Q100 is not applicable (this is an FPGA, not an automotive-grade IC). REACH status should be confirmed with the latest Intel product declaration.
