EP2AGZ350HF40C2N - Arria II GZ FPGA, 350K LEs | Altera | FBGA-1517
MPN: EP2AGZ350HF40C2N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3250 | $3,250.00 |
| 10 | $3090 | $30,900.00 |
| 100 | $2920 | $292,000.00 |
| 500 | $2780 | $1,390,000.00 |
| 1,000 | $2645 | $2,645,000.00 |
EP2AGZ350HF40C2N Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose logic fabric, interconnect, and I/O behavior can be redefined by the user after manufacturing. FPGAs sit hierarchically within programmable logic devices (PLD) -> logic ICs -> integrated circuits. They are favored over fixed-function chips when designs require high parallelism, fast time-to-market, hardware-level reconfigurability, or hardware-accelerated DSP. The Arria II GZ sub-family specifically targets applications that need a balanced mix of logic density, on-chip memory, DSP throughput, and multi-gigabit serial transceivers without moving to the higher-cost Stratix family.
Key features of the EP2AGZ350HF40C2N include 350K logic elements (LEs), roughly 20 Mbits of embedded memory, dedicated 18x18 multipliers for DSP, transceivers reaching 6.375 Gbps, and a configurable I/O subsystem supporting multiple single-ended and differential I/O standards. Operating temperature grade is commercial (0C to +85C) as indicated by the C speed-grade and N suffix, and the device is built on a 40nm low-power process node.
The HF40 package (1517-pin FCBGA, 40mm x 40mm body) integrates high-speed serial links, parallel I/O, external memory interfaces (DDR3, QDR II+, RLDRAM II), and general-purpose logic. Compared with Arria II GX parts, the GZ sub-family typically carries higher logic density and a richer transceiver feature set, which makes this device well suited to high-bandwidth data-path designs.
Typical applications include high-speed serial interface bridging, telecommunications line cards, wireless baseband processing, video processing pipelines, and ASIC prototyping. The combination of transceivers and DSP blocks also enables use in software-defined radio (SDR) front ends and medical imaging accelerators.
When designing with the EP2AGZ350HF40C2N, pay close attention to PCB layout of the 1517-ball FCBGA: a multi-layer board with controlled-impedance routing is required for the transceiver channels, and proper power decoupling is essential. Designers should use the Quartus II design suite with a license supporting the Arria II GZ device family.
This page synthesizes distributor pricing, drop-in compatible Arria II GZ variants, and practical design notes that go beyond the device handbook to help engineers source and integrate this FPGA confidently.
Drop-in alternatives for EP2AGZ350HF40C2N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350HF40C2N (same form factor and footprint) β differing in Package, Logic Elements, Speed Grade, Transceivers, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGZ350HF40C3N
β Drop-Inβ In Stock
$2150 / Unit
View Datasheet βEP2AGZ350HF40C4N
β Drop-Inβ In Stock
$3540 / Unit
View Datasheet βEP2AGZ300HF40C3N
β Drop-Inβ In Stock
$3623.45 / Unit
View Datasheet βEP2AGZ225HF40C3N
β Drop-Inβ In Stock
$1820 / Unit
View Datasheet βEP2AGZ350FH29C3N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1920 / Unit
View Datasheet βEP2AGX260FF35C5G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1395 / Unit
View Datasheet βEP2AGZ350HF40C2N Maximum Ratings & Electrical Characteristics
| Family | Arria II GZ |
| Logic Elements | 350,000 |
| Embedded Memory | approximately 20 Mbits |
| DSP Blocks | Dedicated 18x18 multipliers |
| Transceivers | Up to 16 channels |
| Transceiver Data Rate | Up to 6.375 Gbps |
| Package | 1517-ball FCBGA (HF40), 40 mm x 40 mm |
| Speed Grade | C2 (commercial) |
| Operating Temperature | 0C to +85C (commercial, per N suffix) |
| Process Node | 40 nm low-power |
| I/O Standards | LVDS, LVCMOS, SSTL, HSTL, differential standards |
| External Memory Support | DDR3, QDR II+, RLDRAM II |
| Configuration Method | Quartus II design suite, JTAG, passive/active serial |
| RoHS Status | Compliant (per product listing) |
| Mounting Type | Surface Mount (FCBGA) |
EP2AGZ350HF40C2N Pin Configuration
| Pin B23 | VCC β Core supply voltage (0.9V typical) |
| Pin D5 | GND β Ground reference |
| Pin F10 | REFCLK_p β Transceiver reference clock positive |
| Pin F11 | REFCLK_n β Transceiver reference clock negative |
| Pin H12 | TX_p[0] β Transceiver channel 0 transmit positive |
| Pin H13 | TX_n[0] β Transceiver channel 0 transmit negative |
| Pin J14 | RX_p[0] β Transceiver channel 0 receive positive |
| Pin J15 | RX_n[0] β Transceiver channel 0 receive negative |
| Pin L2 | IO[0] β General-purpose user I/O bank 0 |
| Pin L3 | IO[1] β General-purpose user I/O bank 0 |
| Pin AB30 | DQS_p β DDR3 differential data strobe positive |
| Pin AB31 | DQS_n β DDR3 differential data strobe negative |
| Pin AE1 | JTAG_TCK β JTAG test clock input |
| Pin AE2 | JTAG_TMS β JTAG test mode select |
| Pin AE3 | JTAG_TDI β JTAG test data input |
| Pin AE4 | JTAG_TDO β JTAG test data output |
| Pin AC40 | nCONFIG β Configuration control (active-low) |
| Pin AD41 | nSTATUS β Configuration status (active-low) |
| Pin AE42 | CONF_DONE β Configuration done indicator |
Typical Applications
EP2AGZ350HF40C2N is suitable for 7 applications: Telecommunications Line Cards, Wireless Baseband Processing, High-Speed Serial Interface Bridging, Video Processing Pipelines, ASIC Prototyping, Industrial Test and Measurement, Software Defined Radio Front Ends.
Telecommunications Line Cards
The EP2AGZ350HF40C2N fits telecommunications line-card designs where 350K logic elements drive protocol bridging and traffic shaping while the integrated 6.375 Gbps transceivers carry CPRI, OBSAI, or Serial RapidIO links to baseband and backhaul. Placed as the central processing element between PHY devices and a network processor, the FPGA absorbs data-path overhead without offloading to ASICs. With C2 speed grade and 20 Mbits embedded memory, the device comfortably buffers line-rate traffic. Power-supply sequencing follows the Arria II GZ handbook recommendation to limit inrush on the 0.9V core rail.
Recommended
Wireless Baseband Processing
In wireless baseband applications the EP2AGZ350HF40C2N serves as a multi-antenna signal-processing engine, leveraging its dedicated 18x18 DSP multipliers to implement FFTs, channelization, and MIMO precoding. The 16 multi-gigabit transceivers connect directly to RF front-end ADCs/DACs and CPRI links to remote radio heads, eliminating external SERDES chips. Operating at 350K logic elements, the device typically hosts multiple antenna streams in parallel with margin for protocol stack overhead. The 40nm low-power process keeps typical baseband board power within thermal envelope.
Recommended
High-Speed Serial Interface Bridging
The EP2AGZ350HF40C2N functions as a protocol-bridging FPGA between incompatible serial standards such as 10 Gigabit Ethernet XAUI, PCIe Gen2, Serial RapidIO, and SFI. Each lane can be configured independently at up to 6.375 Gbps, allowing mixed-protocol aggregation on a single device. The 350K logic-element budget accommodates rate-matching FIFOs, CRC engines, and protocol-state machines in parallel. Compared to using multiple smaller FPGAs, the GZ approach lowers board area and BOM count by combining bridging logic with high-speed SERDES.
Recommended
Video Processing Pipelines
For broadcast and professional video, the EP2AGZ350HF40C2N drives multi-stream SDI ingest, color-space conversion, scaling, and overlay composition. The 350K LEs and 20 Mbits embedded memory support multiple parallel HD/3G-SDI streams with frame buffering, while 6.375 Gbps transceivers handle 3G-SDI directly. On-chip DSP blocks accelerate chroma upsampling and temporal noise reduction. Designers leverage the HF40 package's I/O count to fan out multiple SDI streams plus DDR3 frame buffers in a single device.
Recommended
ASIC Prototyping
Engineers use the EP2AGZ350HF40C2N as an ASIC prototyping vehicle, mapping large RTL designs into its 350K logic elements and leveraging its generous I/O count and multi-gigabit transceivers to emulate real chip I/O. Quartus II synthesis and the TimeQuest timing analyzer deliver ASIC-grade timing analysis. Multiple EP2AGZ350HF40 boards can be tiled for multi-FPGA partitioning of large ASIC designs, with SERDES channels bridging between FPGAs at 6.375 Gbps. This use case often requires the C3 or C4 speed grades for prototype timing closure.
Recommended
Industrial Test and Measurement
In high-end test and measurement instruments, the EP2AGZ350HF40C2N acts as the data-acquisition controller, capturing samples from high-speed ADCs and DACs through its 6.375 Gbps transceivers and processing them in real time on dedicated DSP blocks. The 350K logic elements and 20 Mbits embedded memory support deep capture buffers and complex trigger logic, while commercial-grade C2 speed grade suffices for typical instrument clock rates. Compared with discrete ASIC solutions, this FPGA enables firmware-driven feature upgrades after product release.
Recommended
Software Defined Radio Front Ends
The EP2AGZ350HF40C2N supports SDR front-end designs by combining high-speed transceivers for direct RF sampling with DSP blocks for channelization and demodulation. The 350K logic-element budget implements wideband FFTs, digital down-conversion, and protocol demodulators across multiple simultaneous channels. The HF40 package's 1517 balls provide enough I/O for parallel ADC/DAC interfaces and external memory buses. C2 speed grade is typically sufficient for SDR processing rates, with C3/C4 reserved for multi-channel wideband capture.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350HF40C2N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350HF40C3N | EP2AGZ350HF40C4N | EP2AGZ300HF40C3N | EP2AGZ225HF40C3N | EP2AGX260FF35C5G |
|---|---|---|---|---|---|---|
| Package | 1517-ball FCBGA (HF40), 40x40 mm | 1517-ball FCBGA (HF40) - same | 1517-ball FCBGA (HF40) - same | 1517-ball FCBGA (HF40) - same | 1517-ball FCBGA (HF40) - same | 1152-ball FBGA (FF35) - different |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Logic Elements | 350,000 | 350,000 - same | 350,000 - same | 300,000 (-14%) | 225,000 (-36%) | 260,000 (-26%) |
| Speed Grade | C2 | C3 (faster) | C4 (fastest) | C3 | C3 | C5 (Arria II GX family) |
| Transceiver Data Rate | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 3.75 Gbps (GX family) |
| Embedded Memory (Mbits) | ~20 | ~20 | ~20 | ~17 | ~13 | ~16 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- High-density 350K LE fabric with multi-gigabit transceivers on the same die (vs EP2AGX260FF35C5G)
- Drop-in pin-compatible HF40 1517-ball FCBGA footprint with the EP2AGZ350 family (vs EP2AGZ300HF40C3N)
- C2 speed grade provides lowest-cost entry point in the EP2AGZ350 family (vs EP2AGZ350HF40C4N)
Design Notes
The 1517-ball FCBGA HF40 package requires a high-layer-count PCB (typically 12+ layers) with controlled-impedance routing for the 6.375 Gbps transceiver channels. Use the Arria II GZ device handbook pinout and IBIS models to define stack-up, via geometry, and trace length matching. Power-plane capacitance should be sized per the handbook's PDN (Power Distribution Network) guidelines to minimize core-rail droop during simultaneous switching.
Estimated: At full utilization of 350K LEs and active transceivers, the EP2AGZ350HF40C2N can dissipate approximately 8-12 W. Without a heatsink, the 40x40 mm FCBGA junction-to-ambient thermal resistance (theta_JA) typically requires airflow of at least 200 LFM to maintain junction temperature below 100C. For commercial-grade 0C to +85C operation, deploy a thermal pad or heatsink with thermal vias to inner copper planes. Refer to the Arria II GZ thermal-management application note for measured junction-to-board resistance values.
Do not assume the EP2AGZ350HF40C2N is active for new designs. As of 2026-09-08 this MPN is NRD (Not Recommended for New Designs); Altera recommends migrating to Arria 10 or Cyclone 10 GX families for new programs. Ensure all configuration pins (nCONFIG, nSTATUS, CONF_DONE) are properly pulled per the Arria II GZ handbook during JTAG programming to avoid configuration failures. Use Quartus II software version 13.0 or later for this device, as earlier versions may lack silicon support.
Reference-clock routing for the transceivers must follow the guidelines in the Arria II GZ Transceiver Layout Guidelines application note: route the differential pair with 100 ohm differential impedance, maintain at least 3W spacing from other signals, and avoid layer transitions where possible. The HF40 package assigns specific REFCLK pins; do not swap them with general-purpose I/O because the transceiver PHY expects the dedicated clock path. Decoupling capacitors should be placed as close to each power pin as the footprint allows.
Compliance Information
RoHS and lead-free status confirmed per Altera product listings. REACH compliance and conflict-minerals statements per Altera/Intel product responsibility disclosures. Halogen-free status not explicitly stated in available data. AEC-Q100 not applicable to FPGAs in this commercial-grade product line.
