EP2S90F1020C3 - Stratix II 90K LEs FPGA 1020-BGA | Intel / Altera
MPN: EP2S90F1020C3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $850 | $850.00 |
| 10 | $780 | $7,800.00 |
| 50 | $720 | $36,000.00 |
| 100 | $680 | $68,000.00 |
| 250 | $640 | $160,000.00 |
EP2S90F1020C3 Overview
What is a Stratix II FPGA? The Stratix II family is a high-performance, 90 nm SRAM-based programmable logic family introduced by Altera (now Intel) targeting high-density logic, embedded memory, and DSP-intensive applications. Within the broader hierarchy, FPGAs belong to programmable logic devices (PLDs), which sit inside the integrated circuits > logic ICs category. Stratix II FPGAs added on-chip transceivers, TriMatrix memory blocks, and dedicated DSP blocks, bridging the gap between ASIC integration and the flexibility of programmable logic. EP2S90F1020C3 is positioned as a high-density member of this family, balancing logic capacity with embedded memory and DSP throughput.
Key features include 12 dedicated transceiver channels, embedded multiplier blocks for DSP, TriMatrix embedded memory blocks for distributed and block RAM, and support for external memory interfaces including DDR/DDR2/QDRII/RLDRAM. The device operates across commercial and industrial temperature grades (the "C3" speed grade denotes a specific performance bin), and is supported by the Quartus II / Quartus Prime design toolchain for HDL synthesis, place-and-route, and timing closure.
The Stratix II architecture separates logic, routing, and memory into distinct hierarchical layers: each LAB (Logic Array Block) contains 16 Adaptive Logic Modules (ALMs) that combine LUT-based logic with full-adder and register resources, while embedded DSP blocks implement 9-bit / 18-bit / 36-bit multipliers with optional accumulation, and TriMatrix memory provides three block sizes (M512, M4K, M-RAM) tuned for different on-chip buffering workloads.
Typical applications include high-performance digital signal processing (radar, software defined radio), high-speed data acquisition, ASIC prototyping, video and image processing, and telecom baseband processing. The 1020-pin FC-FBGA package supports the high I/O count required for parallel external memory buses and multiple high-speed serial links.
When designing with EP2S90F1020C3, ensure that PCB layout accommodates the 1.0 mm (or finer) BGA pitch with proper microvia/stacked-via stackups and matched-length differential routing for transceiver channels. Power-rail decoupling must follow the Stratix II PDN (Power Distribution Network) guidelines published in the family handbook, and unused transceiver pins must be left open per AN 366: Altera Transceiver Guidelines.
This page synthesizes distributor pricing, drop-in alternative MPNs from the same Stratix II family, and practical design notes not found in a single manufacturer datasheet - providing AEO/GEO-ready content for engineers evaluating the EP2S90F1020C3 for new designs or EOL redesigns.
Drop-in alternatives for EP2S90F1020C3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020C3 (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Logic Array Blocks (LABs), Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1020C4
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1325 / Unit
View Datasheet →EP2S90F1020C5
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1450 / Unit
View Datasheet →EP2S130F1020C3
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1295 / Unit
View Datasheet →EP2S180F1020C3
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1280 / Unit
View Datasheet →EP2S60F1020C3
✅ Drop-In✓ In Stock
$1380 / Unit
View Datasheet →EP2S90F1020C3 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements (LEs) | 90,960 |
| Adaptive Logic Modules (ALMs) | 36,384 |
| Logic Array Blocks (LABs) | 4,548 |
| Embedded Memory (RAM bits) | 4,520,488 (~4.5 Mbit) |
| Maximum User I/Os | 758 |
| Embedded Multipliers (18x18) | 384 |
| Embedded DSP Blocks | 48 |
| Transceiver Channels | 12 |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Maximum Internal Clock Frequency | 816.99 MHz (family maximum) |
| Package | 1020-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature (Speed Grade) | C3 (commercial speed grade) |
| Lead-Free / RoHS | Per Altera/Intel product page |
| Design Toolchain | Quartus II / Quartus Prime |
EP2S90F1020C3 1020-pin fc-fbga (flip-chip fine-pitch bga) Pin Configuration Guide
Pin configuration for EP2S90F1020C3 (1020-pin fc-fbga (flip-chip fine-pitch bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1020C3.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1020C3 is suitable for 6 applications: High-Performance DSP (Radar / SDR), Telecom Baseband Processing, High-Speed Data Acquisition Systems, ASIC Prototyping, Video and Image Processing, Industrial Test & Measurement.
High-Performance DSP (Radar / SDR)
The EP2S90F1020C3 fits high-performance DSP applications such as radar signal processing and software-defined radio (SDR) where 384 dedicated 18x18 multipliers and 48 DSP blocks deliver hundreds of GMACs of throughput. Its 90 nm Stratix II fabric sustains Fmax in the 300-500 MHz range on DSP-heavy paths, while 4.5 Mbit TriMatrix memory buffers FFT bins between stages. The 12 transceiver channels support multiple ADC/DAC links at gigabit speeds. Compared with general-purpose DSP, the FPGA's parallel architecture outperforms sequential DSP processors on streaming workloads by 10x-100x, making it a common choice for phased-array radar beamforming and wideband SDR baseband.
Recommended
Telecom Baseband Processing
For telecom baseband processing (LTE/UMTS/WiMAX), the EP2S90F1020C3 supplies 758 user I/Os for parallel connection to DSP coprocessors, network framer ICs, and CPRI/OBSAI links. The 1020-BGA FC-FBGA package supports the high pin count required for multi-standard macro base stations. TriMatrix memory blocks implement rate-matching buffers and HARQ queues without external SRAM. The 12 transceivers handle CPRI links up to 3.125 Gbps to remote radio heads (RRH), supporting distributed base station architectures. Quartus II IP cores for Turbo decoding, Viterbi, and FFT shorten development cycles for baseband PHY designs.
Recommended
High-Speed Data Acquisition Systems
In high-speed data acquisition systems, the EP2S90F1020C3 sits downstream of multi-channel ADCs to perform real-time channel aggregation, filtering, and storage. The 758 user I/Os accept LVDS/LVCMOS parallel ADC outputs from multiple converters (e.g., 4x AD9245 at 80 MSPS = 640 parallel bits), while TriMatrix memory implements windowed FIR filters. The 12 transceivers stream digitized data to a host processor at multi-gigabit rates. The 90 nm process provides deterministic timing closure for sub-nanosecond skew control across parallel data lanes, which is essential for time-interleaved ADC systems.
Recommended
ASIC Prototyping
ASIC prototyping with the EP2S90F1020C3 enables pre-silicon validation of complex ASIC RTL by leveraging 90,960 logic elements, 4.5 Mbit embedded RAM, and Quartus II synthesis compatibility with industry-standard Verilog/VHDL. The 1020-BGA FC-FBGA package exposes sufficient user I/Os to map ASIC pad-limited designs. Compared to ASIC NRE ($1M+ mask cost) and 12-week tape-out cycles, FPGAs deliver same-day programmable prototypes, supporting software development and system validation pre-silicon. Multiple FPGAs can be tiled via LVDS or transceiver channels to prototype ASICs exceeding 90K LEs.
Recommended
Video and Image Processing
The EP2S90F1020C3 accelerates video and image processing pipelines such as H.264 encode/decode, motion estimation, and color-space conversion. Embedded DSP blocks handle 18x18 multiplications required for DCT/IDCT transforms at full HD (1920x1080) resolutions, while TriMatrix memory stores frame buffers and reference pictures. The 758 user I/Os support multiple HDMI/DVI/DisplayPort interfaces or camera sensor links. Quartus II Video and Image Processing (VIP) suite provides ready-made IP cores that map efficiently onto Stratix II DSP blocks, accelerating time-to-market for video surveillance and broadcast equipment.
Recommended
Industrial Test & Measurement
Industrial test and measurement instruments (protocol analyzers, ATE, oscilloscopes) use the EP2S90F1020C3 to implement real-time pattern matching, protocol decoding, and high-speed stimulus generation. The 4.5 Mbit embedded RAM buffers captured waveform data before upload to host software, while 12 transceivers handle multi-lane protocols (PCIe Gen1, SATA, XAUI). The 758 user I/Os support parallel stimulus/response buses to DUTs. Industrial temperature operation (-40C to +85C, speed grade I variants) makes it suitable for factory-floor equipment. Quartus II SignalTap II logic analyzer IP provides on-chip debugging without external scopes.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020C3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020C4 | EP2S90F1020C5 | EP2S130F1020C3 | EP2S180F1020C3 | EP2S60F1020C3 |
|---|---|---|---|---|---|---|
| Package | 1020-pin FC-FBGA | 1020-pin FC-FBGA - same | 1020-pin FC-FBGA - same | 1020-pin FC-FBGA - same | 1020-pin FC-FBGA - same | 1020-pin FC-FBGA - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements (LEs) | 90,960 | 90,960 | 90,960 | 132,540 | 179,400 | 60,440 |
| Embedded Memory (RAM bits) | 4,520,488 | 4,520,488 | 4,520,488 | 6,747,840 | 9,383,040 | 2,544,192 |
| User I/Os | 758 | 758 | 758 | 758 | 742 | 718 |
| Embedded Multipliers (18x18) | 384 | 384 | 384 | 504 | 768 | 144 |
| Transceiver Channels | 12 | 12 | 12 | 12 | 16 | 12 |
| Speed Grade | C3 (commercial) | C4 (faster) | C5 (fastest) | C3 | C3 | C3 |
Key Differentiators
- Stratix II family - 12 embedded transceivers on a 90 nm high-density fabric (vs EP2S60F1020C3 (Stratix II 60))
- Drop-in speed grade upgrade path within F1020 footprint (vs EP2S90F1020C5)
- Migration path to higher-density Stratix II within same 1020-BGA (vs EP2S180F1020C3)
Design Notes
The 1020-pin FC-FBGA package uses fine-pitch ball grid array (typically 1.0 mm pitch) requiring PCB stackup with microvias and stacked-via construction. Per the Stratix II Handbook (SII51002) PCB layout guidelines, allocate at least 6 PCB layers (4 signal + 2 power/ground planes), use a high-Tg (>=170C) FR-4 or low-loss PCB material, and follow JEDEC JESD51 for thermal via arrays under the BGA thermal balls. Signal integrity simulations with 3D EM tools (HFSS, Cadence Clarity) are recommended for transceiver channel breakouts.
Estimated: At full utilization (90K LEs @ 80% toggle rate, 12 transceivers active), the EP2S90F1020C3 dissipates approximately 10-15 W. With FC-FBGA package theta_JA around 14 C/W (with thermal vias) at still air, junction temperature can rise 140-210C above ambient. A heatsink with thermal interface material or 200-400 LFM forced-air cooling is required for reliable operation. The Quartus II PowerPlay tool provides per-design thermal analysis; derate to commercial (0-85C) or industrial (-40-100C) temperature grades accordingly.
Do not substitute a Stratix II device in a Stratix III/IV/10 footprint - pinout, transceiver count, voltage, and IO standard support differ. Always verify Configuration mode (Passive Serial, Fast Passive Parallel, JTAG) wiring per the Stratix II Configuration Handbook. Unused transceiver channels must be left open per AN 366 (Altera Transceiver Guidelines). The EP2S90F1020C3 is in the Stratix II family with 12 transceivers; confusing with EP2S90F1508 (1508-BGA) will fail PCB fit.
Match transceiver differential pairs to within 5 mils (0.13 mm) of length, maintain 100 ohm differential impedance, and use AC-coupling capacitors (100 nF) on each serial pin. For LVDS data and clock, use 100 ohm differential + common-mode termination networks at the receiver. Reference the Stratix II Selectable IO Standards chapter in the device handbook for SSTL, HSTL, and LVDS termination recommendations. Keep high-speed traces away from noisy power switching nodes and use guard traces or ground shielding for EMI suppression.
Compliance Information
RoHS and lead-free confirmed per Altera/Intel product page. Halogen-free FC-FBGA package. Not AEC-Q100 qualified - choose industrial-grade or automotive-grade Stratix IV/V variants for automotive applications. Lifecycle is obsolete as of 2026 - plan migration to current generation.
