EP2S90F1020C4N - Stratix II FPGA 90K LEs 1020-FBGA | Intel
MPN: EP2S90F1020C4N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1734 | $1,734.00 |
| 5 | $1620 | $8,100.00 |
| 10 | $1530 | $15,300.00 |
| 25 | $1440 | $36,000.00 |
| 100 | $1320 | $132,000.00 |
EP2S90F1020C4N Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs/LABs), programmable routing, and dedicated hard-IP such as DSP blocks, M512/M4K/M-RAM memory blocks, PLLs, and high-speed transceivers. FPGAs sit at the top of the programmable-logic hierarchy, alongside CPLDs, and are widely used as prototyping platforms or as production silicon when design volumes do not justify an ASIC. The Stratix II family specifically introduced the adaptive logic module (ALM) architecture that improves logic packing versus earlier ALM-free families like Stratix.
Key features include 4,520,488 bits of embedded memory, embedded DSP blocks for fixed- and floating-point math, up to 12 transceivers on selected variants, dedicated external-memory interface controllers (DDR/DDR2/QDRII), and 1.2 V core operation with separate VCCIO banks for mixed-voltage I/O. The 1020-pin FC-FBGA package exposes the maximum I/O count in the EP2S90 family and supports JTAG-based configuration via passive, active, or JTAG modes with the EPC configuration devices.
Architecturally, the Stratix II ALM combines an 8-input fracturable look-up table with dedicated adders, registers, and carry chains, allowing the fabric to map dense random logic more efficiently than 4-input-LUT predecessors. Hard IP (DSP, TriMatrix memory, PLLs) is interleaved across the fabric, giving deterministic latency for DSP and memory-intensive designs.
Typical applications include ASIC prototyping and emulation, high-performance DSP for wireless baseband and radar, video processing and broadcast equipment, high-speed serial protocol bridging, and military/aerospace signal processing. The wide I/O count also suits memory-mapped backplane designs.
When designing with EP2S90F1020C4N, plan power-decoupling for the 1.2 V core rail carefully and follow the Stratix II pin connection guidelines for unused I/O banks; the FC-FBGA requires multi-layer PCB with microvia technology for breakout.
This page consolidates distributor stock, lifecycle status, and drop-in same-family alternatives into one engineering-focused reference not provided by the manufacturer datasheet alone.
Drop-in alternatives for EP2S90F1020C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020C4N (same form factor and footprint) β differing in Package, Operating Temperature, Speed Grade, Embedded DSP Blocks, Logic Array Blocks (LABs).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90F1020C4
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View Datasheet βEP2S90F1020C3N
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View Datasheet βEP2S90F1020C3
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View Datasheet βEP2S90F1020I4N
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View Datasheet βEP2S130F1020C4N
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View Datasheet βEP2S60F1020C4N
β Drop-Inβ In Stock
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View Datasheet βEP2S90F1020C4N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements (LEs) | 90,960 |
| LABs/CLBs | 4,548 |
| Total Memory Bits | 4,520,488 |
| User I/Os | 758 |
| Number of Pins | 1020 |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Maximum Fabric Frequency | 711.24 MHz |
| Operating Temperature Grade | Commercial (C4 suffix) |
| Mounting Type | Surface Mount |
| Configuration Method | JTAG / Passive Serial / Passive Parallel / Active Serial |
| RoHS Status | Compliant |
| Lifecycle Status | Not Recommended for New Designs (NRND) |
EP2S90F1020C4N fc-fbga (flip-chip fine-pitch bga) Pin Configuration Guide
Pin configuration for EP2S90F1020C4N (fc-fbga (flip-chip fine-pitch bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1020C4N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1020C4N is suitable for 7 applications: ASIC Prototyping and Emulation, High-Performance DSP Signal Processing, High-Speed Serial Protocol Bridging, Video Processing and Broadcast Equipment, Military and Aerospace Signal Processing, Test and Measurement Instrumentation, Medical Imaging Data Acquisition.
ASIC Prototyping and Emulation
The EP2S90F1020C4N's 90,960 LEs and 758 user I/Os make it well suited as a single-FPGA ASIC prototype target for designs under ~100K gates. The Stratix II ALM architecture provides good logic packing for synthesizable RTL, and the 1.2 V core at 711 MHz fabric speed preserves timing closure across multi-clock ASIC partitions. Designers typically use SelectMAP configuration with multiple EP2S90F1020C4N devices in parallel for multi-FPGA ASIC emulation flows where the high I/O count allows direct ASIC-to-FPGA pin mapping without external muxing.
Recommended
High-Performance DSP Signal Processing
The EP2S90F1020C4N's dedicated DSP blocks and 711 MHz fabric frequency target fixed- and floating-point DSP workloads including wireless baseband, radar pulse-Doppler processing, and software-defined radio front-ends. With 4,520,488 bits of TriMatrix memory and embedded multiplier-accumulate blocks, the device sustains high tap-count FIR/FFT pipelines without external SRAM bottlenecks. The 758 I/Os accept multi-channel ADC data while preserving LVDS signaling for high-speed data capture and processing in defense and test-instrumentation systems.
Recommended
High-Speed Serial Protocol Bridging
Stratix II devices in this family integrate dedicated serializer-deserializer (SERDES) transceivers supporting protocols such as PCI Express, Serial RapidIO, and Gigabit Ethernet. The EP2S90F1020C4N can therefore act as a protocol bridge between proprietary backplanes and standardized serial fabrics in telecom and broadcast equipment. The 758 user I/Os allow direct connection to legacy parallel buses while the transceivers carry modern serial traffic, eliminating external PHY chips and reducing board area in hybrid-protocol designs.
Recommended
Video Processing and Broadcast Equipment
The 758 I/Os of EP2S90F1020C4N support multi-channel SDI/HD-SDI ingest and the embedded DSP blocks sustain real-time color-space conversion, scaling, and frame-rate conversion in broadcast video pipelines. Stratix II fabric runs at 711 MHz which is sufficient for SDI/ASI rate adaptation and light compression/decompression. The 4,520,488-bit TriMatrix memory holds multiple video frame buffers, allowing broadcast equipment to perform chroma keying and graphics overlay without external DDR memory in cost-sensitive designs.
Recommended
Military and Aerospace Signal Processing
The Stratix II EP2S90 family is widely used in defense electronics for radar, electronic warfare, and SIGINT signal processing where its 711 MHz fabric and 758 I/Os handle wideband IF sampling. For deployed systems, the EP2S90F1020I4N industrial-grade variant of the same silicon extends the temperature range to -40C to +100C, while the commercial EP2S90F1020C4N remains suitable for lab and ground-station prototyping. The 1020-ball FC-FBGA package supports ruggedized board stack-ups with underfill and BGA staking for shock/vibration resilience.
Recommended
Test and Measurement Instrumentation
The EP2S90F1020C4N suits high-end test and measurement equipment such as logic analyzers, protocol analyzers, and arbitrary waveform generators because its 90,960 LEs allow deep capture buffers and the 758 user I/Os accept multi-channel probe inputs. The dedicated DSP blocks accelerate FFT and correlation computations in real-time spectrum analysis, while the TriMatrix memory holds long capture records. The Stratix II ALM architecture also supports mixed-timing capture across asynchronous channels, making the device a common platform in high-end bench instruments.
Recommended
Medical Imaging Data Acquisition
The EP2S90F1020C4N supports ultrasound beamforming, CT image reconstruction front-ends, and MRI receiver signal conditioning where its DSP blocks perform real-time pixel/scan-line processing. The 711 MHz fabric and 4,520,488-bit embedded memory allow multi-channel beamformers to hold channel data on-chip, reducing latency versus external SRAM buffering. The 1020-ball FC-FBGA package provides the I/O density required for parallel ADC interfacing across 16-64 channels in modern cart-based and portable ultrasound systems.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020C4 | EP2S90F1020C3N | EP2S90F1020I4N | EP2S130F1020C4N | EP2S60F1020C4N |
|---|---|---|---|---|---|---|
| Package | FC-FBGA-1020 | FC-FBGA-1020 - same | FC-FBGA-1020 - same | FC-FBGA-1020 - same | FC-FBGA-1020 - same | FC-FBGA-1020 - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements (LEs) | 90,960 | 90,960 | 90,960 | 90,960 | 130,000 | 60,000 |
| Speed Grade | -4 (faster) | -4 | -3 | -4 | -4 | -4 |
| Temperature Grade | Commercial (0C to +85C) | Commercial | Commercial | Industrial (-40C to +100C) | Commercial | Commercial |
| User I/Os | 758 | 758 | 758 | 758 | 758 | 758 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Maximum I/O count in EP2S90 family (vs EP2S90F780 (780-pin package variants))
- Higher density vs same-package lower-density options (vs EP2S60F1020C4N (60K LEs))
- Commercial-grade cost advantage (vs EP2S90F1020I4N (industrial grade))
Design Notes
The EP2S90F1020C4N requires a clean 1.2 V core supply with peak currents exceeding 5 A during configuration and high-utilization DSP operation. Place 220 uF bulk plus 0.1 uF + 10 uF ceramic decoupling distributed around the package perimeter; VCC_PLL and VCCAUX rails must be filtered with ferrite beads. Estimated: a Stratix II EP2S90 design typically draws 3-6 W quiescent with peaks at 8-10 W - heatsinking of the FC-FBGA is required for sustained high-utilization workloads.
The 1020-ball FC-FBGA uses 1.0 mm ball pitch; PCB breakout requires microvia (laser-drilled) technology with at least a 4-1-4 stack-up for signal integrity. Follow the Stratix II pin connection guidelines for unused I/O banks - leave unused I/O pins floating only if JTAG boundary-scan testing is not required. Power plane stitching under the BGA is mandatory; split planes crossing the package cause return-path discontinuities and EMI compliance failures.
Configuration failure modes on EP2S90F1020C4N are commonly caused by incorrect MSEL pin strapping for the chosen configuration mode (AS, PS, PPS, JTAG). Verify nCONFIG pull-up, nSTATUS monitoring, and CONF_DONE timing per the Stratix II configuration handbook before debugging logic. The 1.2 V core MUST ramp within the datasheet-specified monotonic range - slow or ringing power-on ramps cause configuration CRC failures that mimic silicon defects.
Estimated: at maximum logic utilization with all DSP blocks active, the EP2S90F1020C4N can dissipate 8-10 W. The FC-FBGA package theta_JA is approximately 12 C/W with standard 4-layer PCB and 0 LFM airflow, so junction temperature rise is 96-120 C above ambient. For commercial-temperature operation (max 85 C ambient), thermal management via thermal vias under the die and a heatsink is recommended for sustained high-utilization workloads.
Compliance Information
RoHS compliant per Altera/Intel product page. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC. Halogen-free status not specified in verified web data. Lead-free (Pb-free) per the N suffix in MPN.
