EP2S60F672C5N - Stratix II FPGA, 60K LEs, 672-FBGA | Altera
MPN: EP2S60F672C5N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $255 | $2,550.00 |
| 100 | $225 | $22,500.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $170 | $170,000.00 |
EP2S60F672C5N Overview
A Field Programmable Gate Array (FPGA) is a class of programmable logic device that lets engineers implement custom digital circuits using configurable logic blocks (CLBs/LABs), programmable routing, and dedicated silicon resources such as block RAM, DSP blocks, PLLs, and high-speed transceivers. FPGAs occupy the rung between general-purpose microcontrollers (fixed hardware, software-defined behavior) and ASICs (fixed hardware, mask-defined behavior), offering hardware-level parallelism without NRE mask charges. The Stratix II family targets high-performance applications such as DSP, telecom datapath, and high-speed serial I/O.
Key features of the EP2S60F672C5N include: 60,440 LEs for fine-grained logic implementation, 2,544,192 RAM bits (about 311 kbytes) for buffering and FIFO designs, embedded DSP blocks for high-speed multiply-accumulate work, 12 PLLs/DLLs for clock management, and a 492-pin user-I/O count that supports wide parallel buses and multiple industry-standard interfaces. The device is speed-grade 5 (faster than C3/C4 but typically slower than I4/I5 industrial speed grades) and is targeted at commercial temperature operation per the suffix pattern.
The Stratix II architecture replaced the Stratix I logic structure with an adaptive logic module (ALM) - an 8-input fracturable LUT - which improves logic packing efficiency and allows each ALM to implement either a full 7-bit function or two smaller independent functions. Combined with dedicated multiplier blocks, on-chip memory, and high-speed I/O, the EP2S60F672C5N can implement complex DSP pipelines, multi-gigabit serial interfaces (via external PHY), and bus-bridging logic on a single die.
Typical applications include high-speed digital signal processing for communications infrastructure, software-defined radio (SDR) baseband, video processing and image pipelines, ASIC prototyping, and high-bandwidth industrial control. The 672-BGA package supplies the pin density required to bring out 492 user I/Os plus the dedicated configuration, clock, and power pins.
When designing with the EP2S60F672C5N, allocate FPGA I/O banks carefully - each bank has a fixed VCCIO supply that determines the supported I/O standard (LVTTL, LVCMOS, SSTL, LVDS, etc.). Decouple every VCCINT and VCCIO pin with bulk plus high-frequency ceramic capacitors, follow the Altera Stratix II pin connection guidelines for unused pins (tie to defined logic levels, not floating), and use the Quartus II design toolchain (Stratix II device support) for synthesis, place-and-route, and bitstream generation.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single, structured reference for the EP2S60F672C5N.
Drop-in alternatives for EP2S60F672C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672C5N (same form factor and footprint) β differing in Speed Grade, Package, RoHS Status, Operating Temperature, Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S60F672C5
β Drop-Inβ In Stock
$410.85 / Unit
View Datasheet βEP2S60F672C4N
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$325 / Unit
View Datasheet βEP2S60F672C3N
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$1175 / Unit
View Datasheet βEP2S60F672C4
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$1080 / Unit
View Datasheet βEP2S60F672C3
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View Datasheet βEP2S60F672C5N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements (LEs) | 60440 |
| Logic Array Blocks (LABs) | 3022 |
| Embedded Memory (bits) | 2544192 |
| Maximum User I/Os | 492 |
| Process Technology | 90 nm |
| Core Voltage (VCCINT) | 1.2 V |
| Maximum Internal Frequency | 609.76 MHz |
| Package | 672-ball FC-FBGA |
| Mounting Type | Surface Mount |
| Speed Grade | C5 (commercial) |
| Temperature Grade | Commercial |
| RoHS Status | Non-compliant (contains lead, per Altera/Intel EOL notice) |
| Configuration Memory | SRAM-based (volatile, requires external configuration device) |
EP2S60F672C5N 672-ball fc-fbga Pin Configuration Guide
Pin configuration for EP2S60F672C5N (672-ball fc-fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S60F672C5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S60F672C5N is suitable for 6 applications: High-Speed DSP for Telecom Infrastructure, Software-Defined Radio (SDR) Baseband, Video Processing and Image Pipelines, ASIC Prototyping and Emulation, Industrial High-Bandwidth Control Systems, Military and Aerospace Sustainment Programs.
High-Speed DSP for Telecom Infrastructure
The EP2S60F672C5N fits telecom baseband DSP because its 60,440 logic elements combined with embedded multiplier blocks (DSP blocks) and 2,544,192 bits of block RAM can implement multi-channel FIR filters, FFT pipelines, and channelization in parallel. Per the Stratix II Device Handbook, the DSP blocks support 18x18-bit signed multiplication at full core speed, letting the EP2S60 deliver aggregate GMACs suitable for 3G/4G base station channel cards. The 492 user I/Os provide ample parallel bus bandwidth for CPRI or OBSAI fronthaul interfaces. Designers benefit from the device's ALM-based architecture, which improves DSP block utilization by 30-40% over Stratix I when implementing MAC operations.
Recommended
Software-Defined Radio (SDR) Baseband
The EP2S60F672C5N is well suited to SDR baseband processing where reconfigurable hardware accelerates waveform-specific DSP. The 60,440 LEs and dedicated multiplier blocks handle the heavy MAC operations needed for digital down-conversion, pulse shaping, and modulation/demodulation, while the 2.5 Mbit block RAM provides sample buffering and FFT twiddle-factor storage. According to the Stratix II datasheet, the device's ALMs allow efficient implementation of both wide datapath (full-ALM 7-bit function) and narrow control logic (two 4-bit functions per ALM) side by side. The 672-FBGA package exposes enough user I/Os to interface to high-speed ADCs/DACs and gigabit serial links for digital RF.
Recommended
Video Processing and Image Pipelines
The EP2S60F672C5N supports real-time video processing pipelines for broadcast, surveillance, and medical imaging applications. With 60,440 LEs and 2.5 Mbit embedded memory, the device can implement multi-tap video filters, color-space converters, motion estimation, and scaling engines at HD (1080p60) rates. Per the Altera Stratix II handbook, the embedded memory supports dual-port and FIFO modes with independent read/write clocks, ideal for line-buffer architectures used in video pipelines. The 492 user I/Os support parallel DVI/HDMI, Camera Link, and BT.656/1120 interfaces, while internal PLLs generate the precise pixel clocks required for clean video timing.
Recommended
ASIC Prototyping and Emulation
The EP2S60F672C5N is widely used for ASIC and ASSP prototyping because its 60,440 LEs can map multi-million-gate ASIC designs at a useful clock rate for software validation. The Stratix II ALM architecture is well suited to mapping synthesized ASIC netlists, and Quartus II provides Design Partitions and LogicLock regions to manage place-and-route across multiple FPGAs when scaling larger ASICs. Per Altera application notes, the 672-FBGA package's 492 user I/Os are sufficient to break out the ASIC's external buses, JTAG, and clock domains. Designers targeting high-speed validation may need to partition across multiple EP2S60/EP2S90/EP2S130 FPGAs for ASICs above 1.5 M gates.
Recommended
Industrial High-Bandwidth Control Systems
The EP2S60F672C5N fits high-bandwidth industrial control systems such as multi-axis motion controllers, high-speed data acquisition, and machine vision where deterministic, parallel processing is required. With 60,440 LEs, the FPGA can implement multiple PID controllers, encoder interfaces, and EtherCAT or PROFINET protocol stacks simultaneously. The 2,544,192-bit embedded memory supports circular buffers for data logging and the 12 PLLs handle multiple motor/encoder clock domains. According to Altera's industrial IP library, the 672-FBGA package's 492 user I/Os comfortably support multiple parallel encoder inputs (RS-422), analog front-end SPI/parallel interfaces, and gigabit Ethernet MAC connections.
Recommended
Military and Aerospace Sustainment Programs
The EP2S60F672C5N with the 'N' suffix is widely deployed in legacy military and aerospace systems where long sustainment timelines require continued production support. Although the part is obsolete for new commercial designs, Altera/Intel's military product group continues to support Stratix II with extended lead times for qualified programs. Per Altera's military product datasheet, the device's 1.2 V VCCINT, 90 nm CMOS process, and deterministic fabric make it suitable for radar signal processing, electronic warfare subsystems, and avionics databus interfaces. Designers should check the latest Altera military product change notices for any lead-finish transitions.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C5 | EP2S60F672C4N | EP2S60F672C3N | EP2S60F672C4 | EP2S60F672C3 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Logic Elements | 60440 | 60440 | 60440 | 60440 | 60440 | 60440 |
| Embedded Memory (bits) | 2544192 | 2544192 | 2544192 | 2544192 | 2544192 | 2544192 |
| User I/Os | 492 | 492 | 492 | 492 | 492 | 492 |
| Speed Grade | C5 | C5 | C4 (faster) | C3 (faster) | C4 (faster) | C3 (faster) |
| Lead-Free (N suffix) | Yes (N suffix) | No (with lead) | Yes (N suffix) | Yes (N suffix) | No (with lead) | No (with lead) |
| Process Technology | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
Key Differentiators
- Speed grade C5 (slowest commercial) versus faster C3/C4 alternatives (vs EP2S60F672C3N)
- Lead-free N suffix versus with-lead bare-C5 (vs EP2S60F672C5)
- 672-ball FC-FBGA package versus larger 1020-ball FBGA (vs EP2S60F1020C5N)
Design Notes
The EP2S60F672C5N requires multiple separate power rails: VCCINT (1.2 V core), VCCIO (per I/O bank, 1.2 V-3.3 V), VCCA_PLL (1.2 V analog, filtered through ferrite beads), and VCCPD (1.2 V/2.5 V/3.3 V pre-driver supply for configuration and JTAG I/Os). Per the Altera Stratix II Device Handbook, the VCCINT supply must be capable of delivering up to 2-3 A for full-resource utilization; use a buck converter with 1.5-2x rated current headroom. Decoupling must follow the reference design: bulk capacitors (220-470 uF) on each rail plus 0.1 uF and 0.01 uF ceramics on every VCCINT/VCCIO pin. VCCA_PLL must ramp monotonically with or after VCCINT to prevent latch-up.
The 672-ball FC-FBGA package uses 1.0 mm ball pitch, which requires 0.5 mm (20 mil) PCB trace width and 0.2 mm (8 mil) trace spacing on the escape layer. The fine-line escape is achievable on standard 4-layer FR-4 with microvia stackup or 6-layer with through-via. Per Altera's Stratix II Hardware Reference, the GND plane must be uninterrupted beneath the BGA, and at least 4-6 GND vias should be placed in the inner BGA field for thermal dissipation. Use the Altera-provided board design files (Allegro or Altium) for the exact ball pad pattern, and follow the JEDEC JESD51 thermal measurement guidelines for theta_JA characterization.
Three common pitfalls with the EP2S60F672C5N: (1) JTAG chain issues from missing VCCPD supply - if VCCPD is not powered, JTAG configuration will fail even though the device is in the chain. (2) Floating unused I/O pins cause excessive I/O supply current - Altera recommends tying unused user I/Os to a defined logic level per the 'Pin Connection Guidelines' chapter. (3) Configuration mode mismatch - the MSEL[2:0] pins select AS (active serial), PS (passive serial), JTAG, or Fast AS mode; incorrect MSEL settings cause configuration failure. Use the Quartus II programming tool to verify MSEL strap values match the configuration device (EPCS16, EPCS64, etc.) used on the board.
For high-speed interfaces (DDR SDRAM, LVDS, external gigabit transceivers), the EP2S60F672C5N provides dedicated DQS delay lines and DQ groups for source-synchronous memories and on-chip PLLs for clock alignment. Per Altera application note AN469, set the DQS delay to one-quarter of the clock period for DDR captures and use the PLL's phase-shift capability for fine-tuning. LVDS inputs require 100-ohm differential termination near the FPGA pins; LVDS outputs benefit from a small series resistor (10-33 ohm) for impedance matching. For multi-gigabit serial interfaces, place the external PHY in close proximity to the FPGA's high-speed I/O banks and route length-match all differential pairs to within 0.13 mm (5 mil).
Estimated: at full logic utilization (80% LEs, full DSP blocks, 50% block RAM) with internal switching activity of 25% and 1.2 V VCCINT, the EP2S60F672C5N dissipates approximately 4-6 W. With a 672-FBGA package and a typical 4-layer FR-4 PCB with internal ground planes, theta_JA is approximately 12-15 C/W. A 6 W dissipation in a 14 C/W package yields a junction temperature rise of 84 C above ambient; with a 25 C ambient, Tj = 109 C - well below the 125 C commercial limit but with limited margin. For designs with high switching activity, add a heatsink or thermal via array under the BGA thermal pad region to keep Tj below 100 C.
Compliance Information
Per Altera/Intel EOL documentation, the Stratix II family predates full RoHS transition. The 'N' suffix indicates lead-free solder balls, but the underlying 90 nm CMOS process may include lead-bearing materials. Not AEC-Q100 qualified (commercial grade). Reach compliance per Intel product environmental reporting.
