EP910PI-20T - 24 Macrocell Classic EPLD, 20ns, PDIP-40 | Intel
MPN: EP910PI-20T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.75 | $18.75 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910PI-20T Overview
A Classic EPLD (Erasable Programmable Logic Device) is a member of the early programmable logic family that sits hierarchically between discrete PAL/GAL devices and modern CPLD/FPGA. EPLDs combine multiple AND/OR macrocell arrays with a programmable interconnect and are used to replace dozens of SSI/MSI logic gates in glue-logic applications. The Classic family targets high-speed, low-power logic integration and offers CMOS-compatible I/O, deterministic timing, and one-time or UV-erasable programming.
Key features of the EP910PI-20T include 24 usable macrocells, 48 product-term AND gates feeding shared OR arrays, 12 dedicated input pins, 20 I/O pins, a maximum toggle frequency around 62.5 MHz, 20 ns pin-to-pin propagation delay (tpd) and an industry-standard JEDEC map. It is fabricated in 1.5 micron CMOS EPROM technology, which yields low static power consumption and in-system programmable configuration via a standard EPROM programmer. The PDIP-40 (PI) package is a through-hole form factor that is convenient for prototype, breadboard and legacy industrial systems.
Typical applications include bus decoding and address mapping on 8-bit and 16-bit microprocessor systems, glue logic replacement for legacy 74LS/74F TTL designs, custom state machines, I/O port expansion, and discrete gate integration in industrial controllers. The device's deterministic 20 ns delay makes it a predictable replacement for multiple 74LS-series packages.
When designing with the EP910PI-20T, designers should validate timing against the Altera Classic EPLD datasheet macrocell switching characteristics and derate propagation delay by operating temperature. Note that the PI package has higher lead inductance than surface-mount equivalents, so high-speed outputs above 30 MHz should be evaluated for signal integrity. This page synthesizes distributor pricing, drop-in same-package alternatives (preferring variants on the XAIPART Site MPN list), and practical design notes not found in the original Altera datasheet.
Drop-in alternatives for EP910PI-20T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PI-20T (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Technology, Programming, Propagation Delay (tPD).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910PI-20
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910PI-15T
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910PI-12T
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910PI-25
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910PI-30T
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910PI-20T Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device | EP910 |
| Number of Macrocells | 24 |
| Propagation Delay (tpd) | 20 ns |
| Maximum Toggle Frequency | 62.5 MHz |
| Number of Dedicated Inputs | 12 |
| Number of I/O Pins | 20 |
| Number of Pins | 40 |
| Package | PDIP-40 (PI) |
| Mounting Type | Through-Hole (DIP) |
| Technology | CMOS EPROM (UV-erasable) |
| Programming | Standard EPROM programmer, JEDEC map |
| RoHS Status | unknown |
| Lifecycle Status | Not Recommended for New Designs (NRND) |
EP910PI-20T Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell-driven) |
| Pin 2 | I/O — Bidirectional I/O pin |
| Pin 3 | I/O — Bidirectional I/O pin |
| Pin 4 | I/O — Bidirectional I/O pin |
| Pin 5 | I/O — Bidirectional I/O pin |
| Pin 6 | I/O — Bidirectional I/O pin |
| Pin 7 | I/O — Bidirectional I/O pin |
| Pin 8 | I/O — Bidirectional I/O pin |
| Pin 9 | I/O — Bidirectional I/O pin |
| Pin 10 | I/O — Bidirectional I/O pin |
| Pin 11 | I/O — Bidirectional I/O pin |
| Pin 12 | GND — Ground |
| Pin 13 | IN — Dedicated input pin |
| Pin 14 | IN — Dedicated input pin |
| Pin 15 | IN — Dedicated input pin |
| Pin 16 | IN — Dedicated input pin |
| Pin 17 | IN — Dedicated input pin |
| Pin 18 | IN — Dedicated input pin |
| Pin 19 | IN — Dedicated input pin |
| Pin 20 | IN — Dedicated input pin |
| Pin 21 | IN — Dedicated input pin |
| Pin 22 | IN — Dedicated input pin |
| Pin 23 | IN — Dedicated input pin |
| Pin 24 | GND — Ground |
| Pin 25 | I/O — Bidirectional I/O pin |
| Pin 26 | I/O — Bidirectional I/O pin |
| Pin 27 | I/O — Bidirectional I/O pin |
| Pin 28 | I/O — Bidirectional I/O pin |
| Pin 29 | I/O — Bidirectional I/O pin |
| Pin 30 | I/O — Bidirectional I/O pin |
| Pin 31 | I/O — Bidirectional I/O pin |
| Pin 32 | I/O — Bidirectional I/O pin |
| Pin 33 | I/O — Bidirectional I/O pin |
| Pin 34 | I/O — Bidirectional I/O pin |
| Pin 35 | VCC — +5V power supply |
| Pin 36 | I/O — Bidirectional I/O pin |
| Pin 37 | I/O — Bidirectional I/O pin |
| Pin 38 | I/O — Bidirectional I/O pin |
| Pin 39 | I/O — Bidirectional I/O pin |
| Pin 40 | I/O — Bidirectional I/O pin |
Typical Applications
EP910PI-20T is suitable for 6 applications: Microprocessor Bus Decoder and Address Mapping, TTL Glue Logic Replacement (74LS/74F Series), Custom State Machine Controller, Legacy Industrial Controller I/O Expansion, I/O Port Expander for Microcontroller Systems, Prototype and Education Platform for Programmable Logic.
Microprocessor Bus Decoder and Address Mapping
The EP910PI-20T's 24 macrocells and 20 I/O pins make it well suited for replacing multiple 74LS138/74LS139 decoder packages in 8-bit and 16-bit microprocessor systems. Each macrocell can be programmed as a sum-of-products term with up to 48 product terms feeding the OR array, enabling complex chip-select and address-mapping logic on legacy 8086, 68k and Z80 buses. With a deterministic 20 ns tpd, the part can decode bus addresses synchronously without introducing wait states up to roughly 25 MHz. Place the EP910PI-20T near the bus transceivers on the address-bus routing path, with VCC bypassed by a 0.1 uF ceramic cap within 5 mm of the VCC pin. Companion 74LS245 transceivers and 74LS373 latches complete a typical glue-logic island that this EPLD replaces 1-for-1.
Recommended
TTL Glue Logic Replacement (74LS/74F Series)
Each EP910PI-20T macrocell replaces up to 16 discrete 74LS gates, so a single chip can collapse a board area filled with 74LS00/74LS08/74LS32 packages into one PDIP-40 socket. The 20 ns tpd matches 74LS-series propagation delay closely (74LS is typically 9-15 ns per gate but compounds with 3-5 gate delays), making the EPLD a timing-neutral replacement for multi-level gate networks. Use the part to consolidate decode, latch, and counter logic on legacy industrial controllers where 74LS stock is becoming hard to source. Program the JEDEC map once with a standard EPROM programmer, then drop the chip into the same through-hole footprint as the original 74LS cluster. The CMOS EPROM technology also reduces quiescent current compared to bipolar TTL.
Recommended
Custom State Machine Controller
The EP910PI-20T's 24 macrocells each contain a programmable flip-flop, allowing designers to implement Moore or Mealy state machines with up to 24 state bits without external latches. Per the Altera Classic EPLD datasheet, the macrocell flip-flop supports D, T, JK and SR modes with asynchronous clear, enabling robust state-machine design for industrial controllers and instrumentation. With 20 dedicated I/O pins available, multiple state-machine outputs can be routed directly to relays, drivers, and indicator LEDs. At the 20 ns tpd, the part supports state transition rates up to about 25 MHz, sufficient for legacy control loops. Use the buried macrocell feature to free I/O pins when the state register is internal-only.
Recommended
Legacy Industrial Controller I/O Expansion
Long-life industrial programs (assembly lines, CNC controllers, test fixtures designed in the 1990s) often specify the EP910PI-20T explicitly because the part has been qualified through decades of field deployment. The 40-pin PDIP package is socketable for field replacement and field-upgrade workflows that surface-mount PLCC versions do not support. With 20 I/O pins and 12 dedicated inputs, the EPLD can scan a 32-key keypad matrix, drive a multiplexed 7-segment display, or buffer parallel sensor arrays without external logic. The 20 ns tpd is fast enough for sub-millisecond control loops in PLC-style applications. Maintain a small safety stock of EP910PI-20T units when sustaining such systems, since the part is now NRND and lead times have lengthened.
Recommended
I/O Port Expander for Microcontroller Systems
The EP910PI-20T can be programmed as a port expander for legacy 8051, PIC, or 68HC11 microcontrollers that lack sufficient GPIO for industrial sensor interfacing. With 20 I/O pins and a parallel-readable input structure, the EPLD acts as a single-chip 16-bit or 20-bit expander that decodes address lines from the host MCU and latches data into its on-chip registers. The 20 ns tpd ensures one MCU clock cycle of latency at 25 MHz host operation, transparent to software. Designers can implement bidirectional bus buffers, multiplexed ADC front-ends, or PWM generators in the same EPLD. Use a 74LS373 latch companion if the host expects a bus-hold cycle, otherwise the EPLD's internal registers suffice.
Recommended
Prototype and Education Platform for Programmable Logic
The EP910PI-20T in PDIP-40 through-hole is widely used in university programmable-logic courses because it can be socketed into a breadboard-friendly footprint and erased with a UV eraser. The Altera Classic EPLD family has a well-documented JEDEC programming flow that students can master in a single lab session, and the 24 macrocells are large enough to implement meaningful projects like ALUs, FIFOs, and bus arbiters. The 20 ns tpd is slow enough that students can observe timing behavior on a logic analyzer without GHz-bandwidth equipment. Use the part with a standard EPROM programmer and a JEDEC file generated by the legacy Altera MAX+PLUS II or classic CUPL toolchain to teach fundamental PLD concepts.
Recommended
Recommended Products Summary
Engineering reference data for EP910PI-20T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PI-20 | EP910PI-15T | EP910PI-12T | EP910PI-25 | EP910PI-30T |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PDIP-40 (PI) | PDIP-40 (PI) - same | PDIP-40 (PI) - same | PDIP-40 (PI) - same | PDIP-40 (PI) - same | PDIP-40 (PI) - same |
| Propagation Delay (tpd) | 20 ns | 20 ns | 15 ns | 12 ns | 25 ns | 30 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| I/O Pins | 20 | 20 | 20 | 20 | 20 | 20 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| Carrier | Tape & Reel | Tube | Tape & Reel | Tape & Reel | Tube | Tape & Reel |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Only 20 ns PDIP-40 EPLD with Tape & Reel carrier (vs EP910PI-20)
- Faster speed-grade option available drop-in (vs EP910PI-15T)
- Through-hole PDIP-40 vs surface-mount PLCC-40 (vs EP910PC-20T)
Design Notes
The EP910PI-20T requires a single +5V VCC supply on pin 35 with two GND returns on pins 12 and 24 for low-impedance grounding. Place a 0.1 uF ceramic bypass capacitor within 5 mm of the VCC pin and a 10 uF tantalum bulk capacitor near the PDIP socket to suppress switching transients during simultaneous macrocell toggling. The CMOS EPROM technology yields low static Icc, but dynamic current rises sharply when many outputs toggle simultaneously above 10 MHz - derate VCC noise accordingly.
For reliable programming and erasure, route the EP910PI-20T on a 40-pin PDIP socket (e.g., 3M 40-pin DIP socket) so the quartz window remains accessible for UV erasure in laboratory and rework flows. Keep high-speed traces (above 30 MHz) short and avoid running them parallel to VCC/GND pours to minimize crosstalk into adjacent I/O pins. Provide at least 50 mil clearance between EPLD outputs and sensitive analog signal paths to limit switching noise coupling.
Do not assume the 20 ns tpd holds across the full operating temperature range - consult the Altera Classic EPLD datasheet's derating curves and apply timing margin in critical paths. Programming voltage is normally generated by the EPROM programmer (VPP = 12.5-13V typical for Classic EPLDs); never apply programming voltage to a powered-on device. Finally, note that PI-package lead inductance (~10 nH per pin) may degrade signal integrity above 30 MHz; consider the EP910PC PLCC variant for higher-frequency designs.
Compliance Information
Lifecycle is NRND per Intel/Altera. RoHS, REACH, lead-free and halogen-free status are unknown from the current manufacturer product page; verify the specific lot with the distributor before placing volume orders. AEC-Q100 is not applicable to a 5V logic EPLD.
