Intel

EPF6024ATI144-2N - FLEX 6000 24K Gates 117 I/O PLD | Intel (Altera)

MPN: EPF6024ATI144-2N ✗ End of Life

In Stock Ships in 1-3 business days

3.0 V to 3.6 V (core 2.5 V, I/O 3.3 V PCI-compliant) Vdss TQFP-144 (JEDEC S-PQFP-G144, 0.50 mm pitch) Package -2 Speed

From $14.1 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$28.5	$28.50
10	$24.2	$242.00
100	$19.75	$1,975.00
500	$16.4	$8,200.00
1,000	$14.1	$14,100.00

ℹ️ All prices are in USD

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EPF6024ATI144-2N Overview

The Intel (formerly Altera) EPF6024ATI144-2N is a CMOS Loadable Programmable Logic Device (PLD) from the FLEX 6000 family, delivering 24,000 typical gates in a 144-pin TQFP package. The device provides 4 dedicated inputs, 117 I/O lines, and a 0.50 mm terminal pitch in a JEDEC S-PQFP-G144 outline.

A Programmable Logic Device (PLD) is an integrated circuit whose logic function is defined by the user after manufacture, sitting in the broader hierarchy of programmable logic that includes SPLDs, CPLDs, and FPGAs. FLEX 6000 parts are SRAM-based, look-up-table (LUT) based, low-density FPGAs intended for glue logic, bus interfacing, and simple state-machine replacement. Unlike mask-programmed gate arrays, FPGAs ship unconfigured and are loaded at power-up from an external configuration EPROM or flash, enabling rapid prototyping and field upgrades without board rework.

Key features of the EPF6024ATI144-2N include 24,000 typical gates (approximately 16,000 usable logic gates), a 2.5 V core supply with 3.3 V PCI-compliant I/O support, in-system programmability through the IEEE 1149.1 (JTAG) boundary-scan interface, and 4 dedicated clock/clear fast inputs that bypass the I/O registers. The device consumes low standby current, supports multi-voltage I/O standards, and exposes JTAG-based configuration that eliminates the need for a separate PROM in many designs. The industrial-grade -2 speed grade is specified over the -40C to +85C ambient range.

Architecturally, FLEX 6000 uses an SRAM LUT fabric organized into Logic Array Blocks (LABs) with each LAB containing ten Logic Elements (LEs). Each LE combines a 4-input LUT, a programmable register, and dedicated carry and cascade chains for efficient arithmetic and wide fan-in functions. Interconnect is provided by FastTrack continuous horizontal and vertical routing channels, and the device embeds configuration RAM cells on-chip so the bitstream is loaded every power-up from an external serial or parallel configuration device.

Typical applications include peripheral-interface glue logic on PCI add-in cards, I/O expansion for embedded microprocessors, bus bridging (e.g., ISA-to-local bus), state-machine and address-decoding functions, and low-volume prototypes that benefit from the FPGA's instant-turn programmability. The 117 I/Os comfortably absorb 32-bit datapaths plus control.

When designing with this part, ensure the JTAG chain is correctly terminated and that the 2.5 V/3.3 V rails are decoupled locally. Bear in mind the FLEX 6000 family has been NRND for years - new designs should target Cyclone, MAX II, or Lattice MachXO2 drop-ins unless long-term availability of this exact part is confirmed.

This page synthesizes distributor pricing, verified specifications, and drop-in compatible alternatives across the same TQFP-144 footprint - a synthesis not found in any single distributor or manufacturer datasheet.

Drop-in alternatives for EPF6024ATI144-2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6024ATI144-2N (same form factor and footprint) — differing in Package, Process Technology, RoHS Status, Speed Grade, Operating Temperature.

EPF6016ATI144-2N

Altera

Package: 144-pin TQFP (TQ144, 22 mm × 22 mm)