Altera

EPF6024ATI144-2 - 24K Gate FLEX 6000 FPGA, 117 I/O | Altera

Name: EPF6024ATI144-2 - 24K Gate FLEX 6000 FPGA, 117 I/O | Altera
Brand: Altera
SKU: EPF6024ATI144-2
Price: 21.9 USD
Availability: InStock

MPN: EPF6024ATI144-2 ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss TQFP-144 (1.0 mm pitch, 22x22 mm) Package -2 Speed

From $21.9 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$48.5	$48.50
10	$41.2	$412.00
100	$32.75	$3,275.00
500	$26.4	$13,200.00
1,000	$21.9	$21,900.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EPF6024ATI144-2 Overview

The Altera EPF6024ATI144-2 is a CMOS Loadable Programmable Logic Device (PLD) from the Altera FLEX 6000 family, delivered in a 144-terminal TQFP package with 0.50 mm terminal pitch and a speed grade of -2. The device provides approximately 24,000 typical gates and integrates 4 dedicated inputs plus 117 user I/O lines, enabling dense glue-logic integration and modest data-path prototyping on a single programmable fabric.

A programmable logic device (PLD) is a class of standard semiconductor that allows engineers to implement custom digital logic by programming an on-chip array of logic elements and an interconnect matrix, rather than committing to a fixed-function ASIC. Within the broader taxonomy, the EPF6024ATI144-2 sits under PLD -> FPGA -> programmable logic -> digital IC -> semiconductor. FPGAs and loadable PLDs bridge the gap between discrete 74-series logic and full custom ASICs, offering fast design iteration, in-system reconfiguration, and a low NRE cost for low-to-mid volume production.

Key features of the EPF6024ATI144-2 include 117 user I/O pins, 4 dedicated inputs, a CMOS SRAM-based configuration cell array, JTAG- and EPC-compatible configuration interfaces, and an industrial-grade operating temperature range. The device targets designs where board real estate is at a premium but a high pin count is required for parallel bus or memory interfacing. Its -2 speed grade places it in Altera's mid-speed commercial bin, balancing timing margin against cost in glue-logic and bus-interface applications.

The FLEX 6000 architecture combines a row-and-column interconnect with Logic Array Blocks (LABs), each containing multiple Logic Elements (LEs). Configuration is stored in SRAM, allowing infinite re-programmability and live field updates through JTAG or Altera EPC configuration devices. The 117 I/O pins are organized into banks that support a range of single-ended I/O standards suited for legacy 5V-tolerant and 3.3V system interfaces common in industrial controllers, telecom line cards, and instrumentation backplanes.

Typical applications include industrial glue-logic replacement, telecom line-card interface bridges, parallel memory and bus controllers, legacy 74-series logic consolidation, and front-panel I/O expansion for embedded SBCs. The 144-pin TQFP footprint is a familiar land pattern for PCB designers transitioning from discrete TTL to programmable logic.

When designing with the EPF6024ATI144-2, plan for a 3.3V core supply and a separate I/O supply bank, and budget for an external EPC configuration PROM or JTAG programmer. Decoupling must follow Altera's recommended 0.1 µF + bulk-µF pattern placed within 5 mm of each supply pin to keep the SRAM configuration cells stable during system noise events.

This page synthesizes distributor pricing, drop-in compatible FLEX 6000 alternatives, and practical board-level design notes not consolidated in the manufacturer datasheet alone.

Drop-in alternatives for EPF6024ATI144-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6024ATI144-2 (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, RoHS Status, Speed Grade.

EPF6016ATI144-2

Altera

Package: TQFP-144

Operating Temperature: -40 °C to 100 °C (Industrial)