EPM7128SQI100-15N - 128-Macrocell CPLD, 15ns, PQFP-100 | Intel
MPN: EPM7128SQI100-15N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $7.62 | $76.20 |
| 100 | $6.4 | $640.00 |
| 500 | $5.55 | $2,775.00 |
| 1,000 | $4.85 | $4,850.00 |
EPM7128SQI100-15N Overview
What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic semiconductor that combines multiple PAL/GAL macrocell arrays with a central interconnect matrix, retaining configuration in on-chip EEPROM or flash memory. CPLDs sit in the broader taxonomy of programmable logic devices (PLDs) alongside simple PLDs (SPLDs), FPGAs, and structured ASICs, and are typically chosen over FPGAs for glue-logic, bus-interface bridging, state-machine and power-up sequencing tasks where deterministic timing and instant-on behavior matter more than raw logic density. As a member of the MAX 7000S family, the EPM7128SQI100-15N targets logic densities up to 2,500 usable gates with the deterministic timing that characterizes this product line.
Key features that differentiate the EPM7128SQI100-15N include the 128-macrocell logic capacity, the dual-voltage I/O capability (3.3 V / 5 V) provided by the MAX 7000S output structure, the 15 ns propagation delay suitable for 66 MHz PCI and similar bus interfaces, and the non-volatile in-system programmability via the JTAG-compatible IEEE 1149.1 boundary-scan interface. The 'S' suffix denotes the MAX 7000S sub-family, while the 'I' industrial temperature range and 'N' lead-free lead finish mark identify the specific orderable part number. Compared with older MAX 7000 variants, the 'S' family reduces power consumption and adds JTAG support.
Architecturally, the device combines four logic array blocks (LABs) interconnected by a programmable interconnect array (PIA), with each LAB containing 16 macrocells. Each macrocell integrates a programmable AND/OR array, a product-term select matrix, a flip-flop, and an I/O control block supporting configurable slew rate, open-drain, and registered/combinational modes. The in-system EEPROM configuration cell technology provides instant-on behavior at power-up with no external boot PROM required, a key advantage versus SRAM-based FPGAs for industrial control and avionics applications.
Typical applications include PCI bus-interface glue logic, microprogrammed state-machine controllers, address decoding and chip-select generation in microprocessor systems, power-supply sequencing logic, industrial motor-control state machines, and legacy board-level replacement of discrete TTL/CMOS glue. Because the device is non-volatile, it is well suited to safety-critical or deterministic-startup applications where a configuration bitstream cannot be lost.
Designers should budget adequate 5 V core current (typically tens of milliamps quiescent, plus dynamic current proportional to toggle rate), place 0.1 µF / 10 µF decoupling close to each VCC/GND pair on the PQFP-100 footprint, and follow Altera/Intel AN70 (MAX 7000S family) application-note guidance for in-system programming and JTAG chain termination. Verify timing against the most recent Intel MAX 7000 device datasheet, not legacy Altera revisions, because part numbering has remained stable but specifications have been re-baselined.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that go beyond a single datasheet excerpt, helping engineers rapidly decide whether the EPM7128SQI100-15N is the right MAX 7000S member for a 15 ns, 128-macrocell industrial design in PQFP-100.
Drop-in alternatives for EPM7128SQI100-15N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM7128SQI100-15N (same form factor and footprint) — differing in Package, Logic Array Blocks (LABs), Operating Temperature, Usable Gates, Device Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128SQI100-10N
✅ Drop-In✓ In Stock
$15.9 / Unit
View Datasheet →EPM7128SQC100-15N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128SQC100-15
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →EPM7128EQI100-15
✅ Drop-In✓ In Stock
$32.75 / Unit
View Datasheet →EPM7128SQI100-15N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | EE-PLD / CPLD |
| Macrocells | 128 |
| User I/Os | 80 |
| Usable Gates | 2,500 (typical) |
| Propagation Delay (tPD) | 15 ns |
| Maximum Frequency (fCNT) | 76.9 MHz |
| Core Supply Voltage (VCCINT) | 4.5 V to 5.5 V |
| I/O Logic Levels | 3.3 V or 5 V (multi-volt I/O) |
| Operating Temperature Grade | Industrial (-40C to +85C) |
| Package | PQFP-100 (R-PQFP-G100) |
| Terminal Form | Gull Wing |
| Package Code | QFP |
| Mounting Type | Surface Mount |
| Process Technology | CMOS |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Non-volatile Configuration | EEPROM (instant-on) |
| RoHS Status | Lead-free (N suffix) |
EPM7128SQI100-15N qfp Pin Configuration Guide
Pin configuration for EPM7128SQI100-15N (qfp package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM7128SQI100-15N.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM7128SQI100-15N is suitable for 7 applications: PCI Bus Interface Glue Logic, Microprocessor Address Decoding and Chip-Select Generation, Industrial Motor-Control State Machines, Power-Supply Sequencing and Supervisory Logic, Legacy TTL/CMOS Glue Logic Replacement, Avionics and Defense Bus Interface, Test and Measurement Instrumentation Front-End.
PCI Bus Interface Glue Logic
The EPM7128SQI100-15N's 15 ns tPD and 76.9 MHz fCNT map cleanly to 33 MHz / 66 MHz PCI timing budgets, where deterministic combinational delay is essential for bus arbitration, address decoding, and command-handling glue between a host controller and peripheral devices. With 128 macrocells it can hold a full PCI target state machine plus chip-select decoding for several downstream peripherals on one device. Multi-volt I/O (3.3 V / 5 V) lets it bridge legacy 5 V peripherals to a 3.3 V host. Designers typically instantiate LABs to build registered command decoders and 32-bit parity generators. The instant-on EEPROM configuration is a key advantage: the device comes out of reset in a known valid state, eliminating the FPGA-style boot latency that would otherwise delay bus enumeration.
Recommended
Microprocessor Address Decoding and Chip-Select Generation
Address decoding and chip-select generation is the classic CPLD use case, and the EPM7128SQI100-15N is well suited with 128 macrocells and 80 I/Os that can fan out to dozens of peripherals in a 16-bit or 32-bit microprocessor system. Designers map memory regions to chip-select lines with full address-decoder logic, plus wait-state generators and bus-arbiter glue. The 15 ns tPD fits the access-time budget of most SRAM and peripheral devices, and the multi-volt I/O makes it compatible with both 3.3 V and 5 V peripherals. The non-volatile configuration means the decode map is in place at power-up, before any boot ROM executes, which is critical for deterministic system bring-up.
Recommended
Industrial Motor-Control State Machines
Industrial motor-control subsystems rely on deterministic state machines for commutation, fault handling, and safety interlocks, and the EPM7128SQI100-15N's industrial temperature grade (-40C to +85C) plus 15 ns tPD match these requirements. With 128 macrocells the device can implement BLDC / stepper commutation tables, encoder quadrature decoders, and PWM enable logic in one chip. Industrial designers benefit from the multi-volt I/O which interfaces directly to 5 V gate drivers and 3.3 V MCUs. The instant-on behavior is critical for safety interlock logic that must be valid before any firmware executes; an FPGA that requires boot-up configuration time would be unsuitable for hard-real-time interlocks.
Recommended
Power-Supply Sequencing and Supervisory Logic
Multi-rail power systems (e.g., FPGAs, SoCs, DDR memory banks) require controlled rail-on / rail-off sequencing to prevent latch-up and in-rush damage. The EPM7128SQI100-15N's 80 I/Os and 128 macrocells can monitor PG (power-good) flags from many regulators and assert ENABLE lines in a programmable order. The 15 ns tPD ensures tight sequencing timing margins, and the 4.5 V to 5.5 V core supply lets the device be powered from an always-on standby rail so sequencing is valid before the main rails come up. Compared with discrete sequencer ICs, the CPLD adds design flexibility without per-channel cost.
Recommended
Legacy TTL/CMOS Glue Logic Replacement
The EPM7128SQI100-15N is widely used to consolidate a board full of discrete 74-series TTL/CMOS glue into one programmable device, replacing dozens of AND / OR / latch packages. With 128 macrocells and 80 I/Os it can typically absorb an entire board's worth of glue logic, dramatically reducing PCB area, BOM count, and assembly cost. Designers port the discrete logic into the MAX 7000S architecture using industry-standard HDL or schematic capture. The industrial temperature grade keeps it viable in factory-floor and outdoor equipment. The non-volatile EEPROM configuration means the replaced board retains its logic through power cycles without external boot memory.
Recommended
Avionics and Defense Bus Interface
Avionics and defense subsystems (MIL-STD-1553, ARINC 429, custom backplanes) demand deterministic timing and instant-on behavior, both of which the EPM7128SQI100-15N provides. With 15 ns tPD and 76.9 MHz fCNT, the device can implement Manchester encoders, parity logic, and timing-recovery state machines for legacy avionics buses. The industrial temperature grade supports the harsh thermal environment of avionics bays. The non-volatile EEPROM configuration guarantees the device is operational before any processor begins to boot, which is mandatory in safety-critical avionics subsystems. The PQFP-100 package is well suited to ruggedized board assembly processes.
Recommended
Test and Measurement Instrumentation Front-End
Test-and-measurement instruments (oscilloscopes, logic analyzers, protocol testers) use CPLDs to handle high-speed trigger logic, channel multiplexing, and pattern generation. The EPM7128SQI100-15N's 80 I/Os make it ideal for fanout from a small number of high-speed comparators to many channel-acquisition paths, while 128 macrocells can host custom trigger state machines. The 15 ns tPD supports trigger latency budgets in mid-range oscilloscopes, and the multi-volt I/O interfaces with both legacy 5 V and modern 3.3 V analog front-ends. The instant-on behavior ensures the instrument is ready immediately at power-up, with no FPGA-style boot delay visible to the user.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQI100-15N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQI100-10N | EPM7128SQC100-15N | EPM7128SQC100-15 | EPM7128EQI100-15 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-100 | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 80 | 80 | 80 | 80 | 84 |
| Propagation Delay (tPD) | 15 ns | 10 ns (-33%) | 15 ns (same) | 15 ns (same) | 15 ns (same) |
| Maximum Frequency (fCNT) | 76.9 MHz | 100 MHz (+30%) | 76.9 MHz (same) | 76.9 MHz (same) | 76.9 MHz (same) |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Sub-Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E |
| Lead-Free Finish | Yes (N suffix) | Yes | Yes | No | No |
Key Differentiators
- Industrial temperature grade with same PQFP-100 footprint as commercial variant (vs EPM7128SQC100-15N)
- 15 ns tPD drops to 10 ns in -10N speed grade at identical footprint (vs EPM7128SQI100-10N)
- MAX 7000S sub-family adds low-power and enhanced JTAG vs MAX 7000E (vs EPM7128EQI100-15)
Design Notes
The EPM7128SQI100-15N draws both quiescent current (typical 15-30 mA at 5 V) and dynamic current proportional to toggle rate. Estimated: at 5 V and an 8-bit bus toggling at 33 MHz, dynamic current adds approximately 5-15 mA, so budget at least 50 mA for VCCINT (5 V) supply and at least 50 mA per bank of I/O toggling. Add 0.1 µF ceramic decoupling at every VCCINT/GND pair on the PQFP-100 footprint, plus a 10 µF bulk tantalum or ceramic close to the package. Do not rely on remote bulk capacitors alone - high-frequency transient current must be served by local ceramics.
Lay out the PQFP-100 footprint with the standard 0.65 mm pitch and 3.2 mm x 3.2 mm package body. Keep all 80 user I/O traces short and impedance-controlled (50 ohm single-ended) for high-speed interfaces; place the JTAG chain header within 5 cm of the TDI/TDO/TCK/TMS pins to avoid noise pickup on boundary-scan signals. Add a 10 kohm pull-up on TCK and TMS per the MAX 7000 datasheet JTAG recommendations, and a 10 kohm pull-down on TDI if the JTAG connector can be left floating in operation. Route GND as a continuous plane under the package and stitch vias around the perimeter for thermal dissipation.
Three pitfalls are common when designing with the EPM7128SQI100-15N. First, do not assume -10N timing margins when you have a -15N part: re-run static timing analysis if you swap grades. Second, the multi-volt I/O pins default to 5 V tolerance on power-up; ensure that 3.3 V peripherals connected to those pins can tolerate a 5 V spike during the cold-start interval (typically <1 ms but board-dependent). Third, the IEEE 1149.1 JTAG chain is not optional - if you leave TMS/TCK floating, the device can enter unintended EXTEST or BYPASS modes; tie them through pull-up / pull-down resistors per AN70.
PQFP-100 gull-wing leads have approximately 25-30 nH of package inductance per pin, which combined with the IO buffer capacitance creates resonances in the 100-200 MHz range. For high-speed buses (66 MHz PCI, parallel RapidIO) place 22 ohm series damping resistors within 5 mm of the CPLD pins and verify signal integrity with TDR measurements on the assembled board. Multi-volt I/O switching between 3.3 V and 5 V thresholds can also generate simultaneous-switching noise (SSN); distribute I/O assignments across the four LABs rather than clustering them so that switching current is balanced across multiple VCCIO/GND pairs.
Compliance Information
Lead-free N-suffix finish confirmed by Intel product naming convention. RoHS / REACH compliance status carried over from MAX 7000 family datasheet and Intel product environmental information. Halogen-free status not explicitly stated in available data.
