10AX090R3F40E2SG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel
MPN: 10AX090R3F40E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6385.14 | $6,385.14 |
| 10 | $6200 | $62,000.00 |
| 100 | $5900 | $590,000.00 |
| 500 | $5650 | $2,825,000.00 |
| 1,000 | $5400 | $5,400,000.00 |
Drop-in alternatives for 10AX090R3F40E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX090R3F40E2LG
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$5750 / Unit
View Datasheet →10AX090R3F40I2SG
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$4133.96 / Unit
View Datasheet →10AX090R2F40E2SG
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$4750 / Unit
View Datasheet →10AX090R2F40E2LG
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$2920 / Unit
View Datasheet →10AX090R2F40E1SG
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$5750 / Unit
View Datasheet →10AX090R2F40I2LG
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View Datasheet →10AX090R1F40I1SG
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$3783 / Unit
View Datasheet →10AX090R3F40E2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 900,000 |
| Adaptive Logic Modules (ALMs) | 339,620 |
| Logic Array Blocks (LABs) | 339,620 |
| Embedded Memory (Bits) | 59,234,304 |
| DSP Blocks | 2,713 (18x19 multipliers) |
| User I/O | 342 |
| Process Technology | 20 nm |
| Core Voltage | 0.85 V |
| Auxiliary Voltage | 0.9 V |
| Speed Grade | -E2 (extended, mid-tier) |
| Temperature Grade | Extended (-40C to +100C) |
| Package | 1517-ball FCBGA, F40 (40x40 mm, 1.0 mm pitch) |
| Mounting Type | Surface Mount (BGA) |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
10AX090R3F40E2SG 1517-ball fcbga, f40 (40x40 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for 10AX090R3F40E2SG (1517-ball fcbga, f40 (40x40 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090R3F40E2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090R3F40E2SG is suitable for 7 applications: 100G/400G Optical Line-Card Data Path, Software Defined Radio (SDR) Baseband, Broadcast 4K/8K Video Processing, Radar Front-End Preprocessing, Medical Imaging Pipeline (CT/MRI), 5G Fronthaul and Backhaul Aggregation, Industrial Test & Measurement Instrumentation.
100G/400G Optical Line-Card Data Path
The 10AX090R3F40E2SG is well suited for 100G and 400G optical line-card data path processing, where 28.05 Gbps GX transceivers drive CFP2/CFP4/QSFP28 optical modules directly. The 900K logic elements and 2,713 DSP blocks provide headroom for MAC framing, OTN framer, FEC (Reed-Solomon RS(255,239) and RS(255,239) KP4), and packet processing pipelines at line rate. The hard PCIe Gen3 x8 block can connect to a host CPU or switch ASIC, while 17.4 Gbps GXB channels support backplane interconnects between line cards. Power dissipation in this role typically runs 25-40W with appropriate heat-sinking on the 40x40 mm FCBGA.
Recommended
Software Defined Radio (SDR) Baseband
In software-defined radio baseband applications, the 10AX090R3F40E2SG's 2,713 DSP blocks with hardened 18x19 multipliers and floating-point operators handle wideband FFT, channelization, and modulation/demodulation for multi-standard wireless systems. The 28.05 Gbps transceivers digitize RF signals from wideband ADC/DAC pairs (such as the AD9234 or AD9144), while the 59 Mbit embedded memory supports large window FFT buffers. Per the Arria 10 device overview, this fabric can implement a 4096-point FFT at >500 MSPS in a single device, enabling LTE, 5G NR, and military waveform processing on a common platform.
Recommended
Broadcast 4K/8K Video Processing
The 10AX090R3F40E2SG handles broadcast 4K and 8K video processing pipelines including HEVC/H.265 and JPEG XS encode/decode, HDR/WCG color space conversion, and SDI I/O aggregation. The 900K logic elements support multi-channel 12G-SDI routers, while the abundant DSP blocks accelerate motion estimation and in-loop filters. The 17.4 Gbps GXB transceivers drive 12G-SDI over coax or fiber, and the 342 user I/O interface to HDMI 2.0/2.1, DisplayPort 1.4, and parallel camera-link inputs. This makes the device ideal for studio routers, OB truck switchers, and post-production color grading systems requiring real-time 8K pipeline.
Recommended
Radar Front-End Preprocessing
For radar front-end preprocessing in phased-array and synthetic aperture radar systems, the 10AX090R3F40E2SG's 28.05 Gbps transceivers digitize wideband IF outputs from A/D converters, while its 2,713 DSP blocks perform pulse compression, MTI filtering, and CFAR detection at real-time rates. The 59 Mbit embedded block RAM stages range-Doppler maps before downstream processing. The extended temperature grade (-40C to +100C junction) supports outdoor or airborne installations. Engineers typically pair this FPGA with multi-channel ADCs like the AD9689 for phased-array sub-arrays.
Recommended
Medical Imaging Pipeline (CT/MRI)
In CT and MRI imaging pipelines, the 10AX090R3F40E2SG accelerates back-projection, iterative reconstruction, and image processing algorithms using its 2,713 DSP blocks with floating-point precision. The 17.4 Gbps GXB transceivers aggregate data from multi-slice detector arrays at line rate, while the 900K logic elements orchestrate DMA into host memory via PCIe Gen3 x8 hard IP. Medical imaging requires deterministic low-latency processing - per Intel's functional safety documentation, the Arria 10 family supports IEC 62304 / IEC 61508 design flows for safety-critical medical applications when paired with appropriate software.
Recommended
5G Fronthaul and Backhaul Aggregation
The 10AX090R3F40E2SG serves as the aggregation FPGA in 5G fronthaul (CPRI/eCPRI) and backhaul (eCPRI, Ethernet, IPsec) equipment. Its 28.05 Gbps GX transceivers interface to 25G/100G Ethernet optical modules, while 17.4 Gbps GXB channels support CPRI Option 7-9 line rates. The 900K logic elements implement MACsec, IPsec, and GTP-U encapsulation at line rate, and the 2,713 DSP blocks accelerate 5G LDPC and Polar FEC decoding. Per O-RAN Alliance specifications, this fabric density comfortably handles 4x 25G eCPRI Class C aggregation in a single device with margin for O-DU low-PHY functions.
Recommended
Industrial Test & Measurement Instrumentation
In high-end oscilloscopes, protocol analyzers, and automated test equipment, the 10AX090R3F40E2SG performs real-time triggering, deep memory capture, and protocol decode on multi-Gbps serial data streams. The 28.05 Gbps transceivers interface to 50 GHz+ ADCs like the AD9207, while 2,713 DSP blocks implement real-time eye-diagram analysis, jitter decomposition (RJ/DJ/PJ), and 64b/66b decoding. The PCIe Gen3 hard IP streams captured waveforms to host CPU for storage and post-processing. Per the Arria 10 datasheet, this FPGA balances cost, density, and transceiver count for mid-range bench-top and modular instrumentation.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090R3F40E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090R3F40E2LG | 10AX090R3F40I2SG | 10AX090R2F40E2SG | 10AX090R2F40E2LG | 10AX090R2F40E1SG |
|---|---|---|---|---|---|---|
| Package | 1517-FCBGA (F40) | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Transceivers | 3 (GX 28.05 Gbps) | 3 (GX 28.05 Gbps) | 3 (GX 28.05 Gbps) | 2 (GX 28.05 Gbps) | 2 (GX 28.05 Gbps) | 2 (GX 28.05 Gbps) |
| Speed Grade | -E2 (extended mid-tier) | -E2 | -I2 | -E2 | -E2 | -E1 (fastest) |
| Temperature Grade | Extended (-40C to +100C) | Extended (-40C to +100C) | Industrial (-40C to +125C) | Extended (-40C to +100C) | Extended (-40C to +100C) | Extended (-40C to +100C) |
| Lead Finish | Pb-free (G) | Leaded (L) | Pb-free (G) | Pb-free (G) | Leaded (L) | Pb-free (G) |
| DSP Blocks | 2,713 | 2,713 | 2,713 | 2,713 | 2,713 | 2,713 |
| Embedded Memory (Mbit) | 59.23 | 59.23 | 59.23 | 59.23 | 59.23 | 59.23 |
| User I/O | 342 | 342 | 342 | 342 | 342 | 342 |
Key Differentiators
- 3-transceiver count vs 2-transceiver R2 variants in same package (vs 10AX090R2F40E2SG)
- Industrial -I2 vs Extended -E2 temperature grade option (vs 10AX090R3F40I2SG)
- Extended vs fastest speed grade tradeoff (vs 10AX090R2F40E1SG)
- 900K logic elements and 2,713 DSP blocks scale-up option (vs 10AS066K2F35E2SG (Arria 10 SoC 10AS066 family))
Design Notes
The 1517-ball FCBGA F40 package uses a 1.0 mm pitch on a 40x40 mm body, requiring high-density interconnect (HDI) PCB technology with micro-via stack-ups. Per Intel's Arria 10 board design guidelines, allocate at least 12 PCB layers (8 signal, 4 power/ground) for transceiver channel break-out, with controlled-impedance 100 ohm differential routing for SERDES lanes and 50 ohm single-ended for CMOS I/O. Use 0.2 mm (8 mil) laser-drilled micro-vias on the BGA pads with filled-and-capped via-in-pad plating to meet the 1.0 mm pitch escape routing. Skim the PCB stack-up against the Intel Arria 10 pin connection guidelines document before tape-out.
The Arria 10 GX requires a multi-rail power distribution network (PDN) with sequencing: 0.85 V core (VCC), 0.9 V auxiliary (VCCA), 1.2 V transceiver (VCCP, VCCR, VCCT), and 1.8 V/2.5 V/3.0 V I/O rails. Per the Arria 10 device datasheet, ramp sequencing must follow the order VCCA -> VCC -> VCCP -> VCCIO to avoid latch-up. Use a dedicated FPGA power sequencer IC (such as the LTC2928 or similar) with PowerGood feedback. Bulk decoupling requires 22 uF to 47 uF tantalum or ceramic capacitors within 1 inch of each BGA power ball cluster, plus 100 nF and 10 nF high-frequency decoupling on every power pin pair.
Estimated: At full logic utilization (90% LE, 80% DSP, all 3 transceivers active), the 10AX090R3F40E2SG dissipates approximately 25-35 W. The F40 package has a junction-to-ambient thermal resistance (theta_JA) of approximately 6 C/W with a 1 m/s airflow heatsink. The recommended thermal solution is a 40x40 mm copper heat spreader with thermal interface material (TIM) and 200 LFM forced airflow. Per Intel's Arria 10 thermal management application note, derate the device if junction temperature exceeds 100 C. Place thermal vias in the PCB BGA land pattern under the central thermal balls for PCB-side heat extraction.
Three common pitfalls in Arria 10 designs: (1) Bitstream compatibility - the configuration bitstream is device-specific; swapping between R2 and R3 transceiver variants requires recompilation in Quartus Prime Pro, not just a different OPN. (2) Transceiver reference clock - per the Arria 10 datasheet, each GX channel requires a clean 100 MHz or 156.25 MHz reference with -80 dBc/Hz phase noise at 100 kHz offset; use a dedicated jitter cleaner like the AD9548. (3) MSL handling - the FCBGA has MSL3 rating (168 hours floor life at <30 C/60% RH); bake at 125 C for 24 hours before assembly if exposure exceeds the floor life.
For 28.05 Gbps GX transceiver channels, follow the Intel Arria 10 GX Transceiver User Guide: route transmit and receive differential pairs with intra-pair skew less than 0.15 mm (6 mil), maintain 100 ohm differential impedance with ground-reference coplanar waveguide (GCPW) stack-up, and keep total channel loss below 12 dB at 14 GHz Nyquist. Use HyperLynx or Ansys HFSS for pre-layout channel modeling. AC-coupling capacitors on transmit lanes should be 100 nF 0402 size with X7R ceramic, placed within 5 mm of the FPGA balls. Reference clock distribution must use a clock buffer with matched-length routing.
Compliance Information
Pb-free (G suffix) per verified distributor data. Industrial-grade variants (I suffix) are NOT automotive AEC-Q100 qualified - they meet industrial temperature and reliability only. Halogen-free status not explicitly confirmed in verified data - see Intel material declaration for IC-grade products. Per Intel product compliance, all Arria 10 GX devices are REACH and RoHS compliant.
