10AX090S2F45E1SG - Arria 10 GX FPGA 900K LE | Intel
MPN: 10AX090S2F45E1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6250 | $6,250.00 |
| 10 | $5980 | $59,800.00 |
| 100 | $5640 | $564,000.00 |
| 500 | $5210 | $2,605,000.00 |
| 1,000 | $4890 | $4,890,000.00 |
Drop-in alternatives for 10AX090S2F45E1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX090S1F45E1SG
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View Datasheet →10AX090S2F45I1SG
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View Datasheet →10AX090N2F45E1SG
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View Datasheet →10AX090N2F45I1SG
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View Datasheet →10AX090N3F45I2SG
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View Datasheet →10AX090N3F45E2LG
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View Datasheet →10AX090S2F45E1SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Device | 10AX090 |
| Logic Elements (LE) | 900,000 |
| Embedded Memory | 59,234,304 bits |
| DSP Blocks | 1,518 (variable-precision, hard floating-point) |
| Transceivers | 24 channels |
| Max Transceiver Data Rate | 12.5 Gbps |
| Package | 1932-ball FCBGA |
| Package Code | F45 |
| Speed Grade | -E1 (fastest) |
| Device Variant | -S2 (lower-power core) |
| Operating Temperature Grade | Extended |
| Process Node | 20 nm TSMC |
| Hard PCIe Gen3 Blocks | Yes, up to 96 lanes |
| Configuration Method | Active serial (AS), Passive serial (PS), JTAG |
| RoHS Status | Compliant |
10AX090S2F45E1SG f45 Pin Configuration Guide
Complete pinout information for 10AX090S2F45E1SG (f45 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090S2F45E1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090S2F45E1SG is suitable for 7 applications: 100G Optical Line-Card Bridging, Wireless Baseband Processing, Military Radar Signal Processing, ASIC Prototyping, Broadcast Video Processing, HPC Acceleration Card, Medical Imaging Processor.
100G Optical Line-Card Bridging
The 10AX090S2F45E1SG's 24 transceivers at 12.5 Gbps aggregate 300 Gbps of bidirectional serial bandwidth, sufficient for 100G Ethernet and OTU4 line-card bridging designs. With 900K LEs and 1,518 DSP blocks, the FPGA can implement MAC, PCS, FEC, and packet-processing functions without external coprocessors. The hard PCIe Gen3 IP block enables direct CPU pairing over x8 PCIe Gen3. Estimated typical power consumption at full transceiver utilization is 22-28 W, requiring a controlled-airflow thermal design.
Recommended
Wireless Baseband Processing
The 10AX090S2F45E1SG targets LTE and 5G NR baseband units where the variable-precision DSP and floating-point hard IP accelerate FFT, channel estimation, and MIMO decoding. The 59 Mbits of embedded memory buffers OFDM symbols efficiently, reducing external DDR4 bandwidth. Twenty-four transceivers support CPRI up to option 7 (9.83 Gbps) for fronthaul, while 12.5 Gbps lanes enable eCPRI and JESD204B to ADCs/DACs. Quartus Prime DSP Builder accelerates floating-point IP generation.
Recommended
Military Radar Signal Processing
The 10AX090S2F45E1SG delivers the logic density and DSP throughput required for phased-array radar beamforming and pulse compression. With 1,518 hard floating-point DSP blocks operating at up to 750 MHz, the device can sustain complex FFT chains at multi-Gsample rates. Transceivers support multi-channel JESD204B ADC/DAC interfaces common in modern radar receivers. Extended temperature grade (E1) suits air-cooled military electronics; ruggedized deployments often derate the industrial I1 variant.
Recommended
ASIC Prototyping
The 10AX090S2F45E1SG is widely used as an ASIC prototyping platform due to its high logic density and large embedded memory. Designers partition ASIC RTL across multiple Arria 10 devices using FPGA-in-the-PCB stacking or pin-multiplexed daughter cards. Quartus Prime supports incremental compilation and Design Partition flow to manage compile time. 1.6 GHz internal clock rates can emulate many ASIC clock domains with limited speed penalty, accelerating pre-tape-out verification.
Recommended
Broadcast Video Processing
The 10AX090S2F45E1SG powers 4K/8K broadcast video routers, multi-channel up/down/cross converters, and live production switchers. Twenty-four transceivers handle SDI (SMPTE 2022, SMPTE 2110) and 12G-SDI inputs/outputs, while 900K LEs implement color space conversion, scaling, and frame-rate conversion pipelines. The 7.4 MByte on-chip memory buffers large video frames for low-latency processing. Extended temperature grade (E1) suits broadcast chassis operating at elevated rack temperatures.
Recommended
HPC Acceleration Card
The 10AX090S2F45E1SG accelerates HPC workloads such as genomics, financial Monte Carlo simulation, and machine learning inference. The PCIe Gen3 x16 hard IP provides 16 GB/s host link bandwidth with sub-microsecond latency. The 900K LEs and 1,518 DSP blocks implement custom dataflow engines optimized for specific algorithms, delivering 2-10x speedups over CPU-only implementations on parallel-friendly kernels. Board thermal designs typically use copper cold plates to remove the 22-28 W envelope.
Recommended
Medical Imaging Processor
The 10AX090S2F45E1SG enables CT, MRI, and ultrasound systems by processing raw high-speed ADC streams into image frames in real time. Its 12.5 Gbps transceivers interface to multi-channel JESD204B ADCs, while the embedded DSP and floating-point IP implement back-projection and beamforming. 900K LEs allow real-time 3D reconstruction at 30-60 fps for clinical workflows. Medical designs typically use the I1 industrial temperature grade variant and follow IEC 60601-1 isolation practices at the board level.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090S2F45E1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090S1F45E1SG | 10AX090S2F45I1SG | 10AX090N2F45E1SG | 10AX090N3F45I2SG | 10AX090N3F45E2LG |
|---|---|---|---|---|---|---|
| Package | F45 (1932-ball FCBGA) | F45 (1932-ball FCBGA) - same | F45 (1932-ball FCBGA) - same | F45 (1932-ball FCBGA) - same | F45 (1932-ball FCBGA) - same | F45 (1932-ball FCBGA) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Core Power Variant | S2 (lower-power) | S1 (baseline) | S2 (lower-power) | N2 (baseline) | N3 (baseline) | N3 (baseline) |
| Speed Grade | -E1 (fastest) | -E1 | -I1 | -E1 | -I2 | -E2 |
| Temperature Grade | Extended | Extended | Industrial | Extended | Industrial | Extended |
| Transceivers | 24 x 12.5 Gbps | 24 x 12.5 Gbps | 24 x 12.5 Gbps | 24 x 12.5 Gbps | 24 x 12.5 Gbps | 24 x 12.5 Gbps |
| Embedded Memory | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits |
Key Differentiators
- Lower-static-power -S2 core variant in identical F45 footprint (vs 10AX090S1F45E1SG)
- 24 hard PCIe Gen3 lanes integrated (vs 10AS066K3F35I2SG)
- Hard floating-point DSP blocks at 1.5 GHz (vs Cyclone 10 GX 10CX220YF780E5G)
Design Notes
Estimated: At typical 900K LE utilization with 12.5 Gbps transceivers active, expect 22-28 W dissipation. Use a copper cold plate or finned heatsink with 1-2 m/s airflow. Apply thermal interface material rated for >3 W/mK conductivity and monitor junction temperature via the on-die temperature diode with the MAX1619 or equivalent external sensor.
Transceiver channel loss budget must remain under 12 dB at 6.25 GHz Nyquist (12.5 Gbps data rate) per the Intel Arria 10 Transceiver User Guide. Use Megtron 6 or similar low-loss PCB material with matched-length differential pairs and AC-coupling capacitors. Verify post-layout simulation against the IBIS-AMI models published in the Quartus Prime installation before tape-out.
The 1932-ball FCBGA requires a 1.0 mm ball pitch and high-density routing of 4-6-6-6 layers minimum. Use microvia-in-pad (VIPPO) stack-up for breakout, and provide continuous ground and power planes below the BGA. Multiple GND balls under the die connect to the internal ground plane via 8-mil stitched vias; do not allow signal traces to interrupt stitching patterns.
Estimated: This device requires at least four power rails (VCC, VCCP, VCCERAM, VCCPT, and transceiver rails). Use a multi-phase PWM controller such as the LTM4677 to achieve sub-1% regulation and minimize switching noise coupling into sensitive transceiver channels. Decoupling must include 100 nF 0201 caps at every VCC ball with a 10 uF bulk per quadrant.
Do not rely solely on software power estimates. Early-board bring-up should measure actual VCC current with a precision shunt monitor. The configuration scheme must match the AS/PS/JTAG selection pins at reset - misconfiguration here is the most common first-time bring-up failure mode. Use Intel's Pin Planner to verify I/O standard assignments before synthesis.
Compliance Information
RoHS and lead-free per Intel product page. Halogen-free status not explicitly stated in retrieved data and marked unknown.
