10AX090N3F45I2LG - Arria 10 GX 900K LE FPGA | Intel FPGA | 28nm
MPN: 10AX090N3F45I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3680 | $36,800.00 |
| 100 | $3450 | $345,000.00 |
| 500 | $3220 | $1,610,000.00 |
| 1,000 | $2995 | $2,995,000.00 |
Drop-in alternatives for 10AX090N3F45I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX090N3F45E2LG
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View Datasheet →10AX090N3F40I2LG
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View Datasheet →10AX090N3F40I2SG
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View Datasheet →10AX090N2F45I2LG
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View Datasheet →10AX090N2F45I2SG
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View Datasheet →10AX090N2F45E2LG
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View Datasheet →10AX090N3F45I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory (bits) | 59,234,304 |
| User I/O Count | 768 |
| Core Voltage | 0.9 V |
| Process Technology | 20 nm |
| Transceiver Data Rate (max) | 28.05 Gbps |
| Number of Transceivers | 24 |
| DSP Blocks | Variable-precision, 1.5 TFLOPS |
| Package | 1932-ball FCBGA |
| Operating Temperature | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount (BGA) |
| PCIe Hard IP | Gen3 x8 |
| Memory Controller Hard IP | DDR4, QDR-IV, RLDRAM3 |
| Configuration | SRAM-based, volatile |
| RoHS Status | Compliant |
10AX090N3F45I2LG Pin Configuration
| Pin A1 | GND — Ground reference |
| Pin A2 | VCC — Core supply (0.9 V) |
| Pin B1 | IO_BANK_1A — I/O bank 1A signal |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090N3F45I2LG is suitable for 6 applications: 100G Optical Line-Card Aggregation, Radar and Electronic-Warfare Signal Processing, Medical Imaging Pipeline, 4K Video Broadcast Encoding, ASIC Prototyping, Wireless Baseband Processing.
100G Optical Line-Card Aggregation
The 10AX090N3F45I2LG fits 100G line-card aggregation because its 24 transceivers at 28.05 Gbps support OTU4, 100GbE, and 32G FC simultaneously. The 900K logic elements hold a full tri-mode 100G MAC plus channelized framing overhead, while 768 I/Os and 12 banks interface to external DDR4 buffers. Compared with a Stratix 10 part, it trades raw fabric speed for lower BOM cost at comparable functional density.
Recommended
Radar and Electronic-Warfare Signal Processing
The 10AX090N3F45I2LG's 1.5 TFLOPS variable-precision DSP throughput and 28 Gbps transceivers make it ideal for radar front-end aggregation and EW processing. A single device can implement FFT, beamforming, and pulse-compression pipelines for phased-array antennas while ingesting ADC samples over multiple JESD204B links. Industrial temperature grading supports outdoor naval and ground-mobile installations.
Recommended
Medical Imaging Pipeline
The 10AX090N3F45I2LG is well suited to CT, MRI, and ultrasound image reconstruction pipelines that demand deterministic latency and high DSP throughput. Its variable-precision DSP blocks accelerate FFT and back-projection kernels, while the 768 I/Os aggregate high-channel-count ADC front-ends via LVDS or JESD204B. Industrial temperature screening ensures reliability in clinical-equipment environments without forced-air cooling.
Recommended
4K Video Broadcast Encoding
The 10AX090N3F45I2LG supports 4K broadcast encoding and transcoding thanks to its high logic density and dedicated DSP blocks for H.264/HEVC motion estimation. Multiple 12G-SDI ingest paths require 28 Gbps transceivers, which this part provides natively. Its industrial temperature rating enables fan-less rack installations in studio environments where acoustic noise is unacceptable.
Recommended
ASIC Prototyping
The 10AX090N3F45I2LG is an effective ASIC prototyping vehicle because its 900K logic elements partition cleanly across multiple child designs via partial reconfiguration. Quartus Prime supports time-domain multiplexing of multiple ASIC blocks, allowing early software development before tape-out. The industrial temperature variant supports prototyping for automotive and industrial ASICs.
Recommended
Wireless Baseband Processing
The 10AX090N3F45I2LG handles LTE and 5G baseband processing, with its high logic density accommodating multi-channel LDPC encoders and FFT chains. The 28 Gbps transceivers interface to high-data-rate fronthaul links (eCPRI, CPRI Option 9), while DDR4 hard memory controllers feed high-bandwidth sample streams. Industrial temperature grading supports outdoor small-cell deployments.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090N3F45I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090N3F45E2LG | 10AX090N3F40I2LG | 10AX090N3F40I2SG | 10AX090N3F40E2LG | 10AX090N2F45I2LG |
|---|---|---|---|---|---|---|
| Package | 1932-ball FCBGA | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Transceiver Max Data Rate | 28.05 Gbps | 28.05 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 28.05 Gbps |
| Speed Grade | N3 | N3 | N3 | N3 | N3 | N2 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +100C) | Industrial (-40C to +100C) |
| User I/O Count | 768 | 768 | 768 | 768 | 768 | 768 |
| Embedded Memory (Mb) | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 |
Key Differentiators
- Highest-density Arria 10 GX at 28 Gbps (vs 10AX066N3F40E1SG)
- Industrial temperature screening at full transceiver speed (vs 10AX090N3F45E2LG)
- N3 speed grade for highest Fmax (vs 10AX090N2F45I2LG)
Design Notes
The 1932-ball FCBGA package requires a high-performance thermal interface. Estimated: at full DSP utilization (1.5 TFLOPS) the die consumes approximately 25-35 W, which the 31x31 mm FCBGA package must dissipate through a heatsink plus thermal interface material. Junction temperature must stay below 100C for industrial-grade reliability; use the Arria 10 thermal model from Intel and de-rate by at least 15C for production margin.
Estimated: at VIN=0.9 V core and full utilization, peak core current can reach 30+ A, which mandates a multi-phase PMIC with sub-milliohm PCB distribution. Use a minimum 8-layer PCB with 2 oz copper on core planes. Sequencing must follow Intel's Power-Up Sequence: 3.3V -> 2.5V -> 1.8V -> 0.9V core within the documented ramp windows; otherwise the part may latch-up.
Use microvia or HDI PCB technology for the 1.0 mm pitch BGA escape. Escape routing through 4 vias-per-ball with via-in-pad plating is recommended for the transceiver banks. Maintain 100-ohm differential impedance for 28 Gbps SerDes lanes and 50-ohm single-ended for GPIO. Place decoupling capacitors within 100 mil of each power pin and use a 0402 footprint to keep the loop area minimal.
Do not substitute Arria 10 GX with Arria 10 GT or SX variants without re-validating the transceiver IP - the protocol hard-IP differs. Also do not use 'E2' commercial parts in industrial designs; the temperature derating will cause field failures. Always use the Quartus Prime pin-assignment file (.qsf) for the exact ordering code, since the same package can have different ball maps across temperature grades.
Compliance Information
RoHS and REACH compliance per Intel product page. Not AEC-Q100 qualified (industrial temperature grade, not automotive). Lead-free matte-tin finish on FCBGA balls.
