10AX115S3F45I2LG - Arria 10 GX FPGA, 1.15M LE, 1932-FCBGA | Altera (Intel)
MPN: 10AX115S3F45I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16500 | $16,500.00 |
| 10 | $15250 | $152,500.00 |
| 25 | $14600 | $365,000.00 |
| 50 | $13950 | $697,500.00 |
| 100 | $13200 | $1,320,000.00 |
Drop-in alternatives for 10AX115S3F45I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115S3F45I2SG
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View Datasheet →10AX115S3F45E2LG
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View Datasheet →10AX115S2F45I2LG
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View Datasheet →10AX115S2F45I2SG
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View Datasheet →10AX115S3F45E2SG
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$6200 / Unit
View Datasheet →10AX115S2F45E2LG
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$7100 / Unit
View Datasheet →10AX115S1F45I1SG
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View Datasheet →10AX115S3F45I2LG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,600 bits (68.86 Mb) |
| User I/O Count | 624 |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Package | 1932-BBGA, FCBGA (F45: 45x45 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial grade) |
| Temperature Grade | Industrial (I2) |
| Speed Grade | 3 (S3) |
| Transceivers | Up to 28.05 Gbps (per Arria 10 GX family) |
| DSP Blocks | Variable-precision (per family) |
| RoHS Status | Compliant (lead-free, LG suffix) |
| Design Tool | Intel Quartus Prime |
10AX115S3F45I2LG 1932-bbga, fcbga (f45: 45x45 mm) Pin Configuration Guide
Complete pinout information for 10AX115S3F45I2LG (1932-bbga, fcbga (f45: 45x45 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115S3F45I2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S3F45I2LG is suitable for 6 applications: 100G/40G Ethernet Line Card, PCIe Gen3 Root Complex / Endpoint, Radar / EW Signal Processing, 4K/UHD Video Processing, ASIC Prototyping, High-Speed Serial Backplane Aggregation.
100G/40G Ethernet Line Card
The 10AX115S3F45I2LG fits 100G/40G Ethernet line-card prototypes because of its up to 28.05 Gbps transceivers and 1.15M logic elements that absorb MAC, PCS, and lookup-table functions. With 624 user I/O, the device can drive multiple QSFP28 cages and external DDR4 memory channels simultaneously. The 20 nm process and 0.9 V core supply reduce dynamic power versus prior 28 nm nodes, an important factor at line-card port densities. Designers use Quartus Prime with the Intel IP catalog to instantiate 100G Ethernet MAC, FEC, and RS-FEC hard IP directly on the transceiver channels. Compared with a Stratix 10 device, the Arria 10 GX is the price-optimized choice when absolute highest DSP performance is not required.
Recommended
PCIe Gen3 Root Complex / Endpoint
The 10AX115S3F45I2LG suits PCIe Gen3 root-complex and endpoint designs because it integrates PCIe Gen3 hard IP blocks alongside the high-speed transceivers needed for x8/x16 link widths. With 1.15M logic elements and 68.86 Mb of embedded memory, the device can host multiple soft cores, DMA engines, and protocol bridges concurrently. Industrial temperature rating (I2 suffix) supports deployment in controlled-environment servers, test equipment, and embedded platforms. Use the Quartus Prime PCIe hard IP wizard to instantiate the endpoint or root-port controller. The Arria 10 family offers a balanced cost-performance point versus Cyclone 10 (too few) and Stratix 10 (over-spec for many Gen3 applications).
Recommended
Radar / EW Signal Processing
The 10AX115S3F45I2LG is well-matched to radar and electronic-warfare signal processing because its variable-precision DSP blocks deliver high TOPS at the 20 nm node, while the transceiver array streams multi-GSPS ADC data into the FPGA fabric. With 1.15M LE and 68.86 Mb of on-chip memory, designers can implement pulse compression, moving-target indication, and adaptive beamforming without external memory for first-stage processing. Industrial temperature rating is appropriate for many ground- and surface-platform installations. The device's 0.9 V core and 20 nm process reduce thermal density relative to 28 nm predecessors. For airborne or extended-temp applications, prefer the E2 variant (10AX115S3F45E2LG).
Recommended
4K/UHD Video Processing
The 10AX115S3F45I2LG fits 4K/UHD video processing because its wide memory bandwidth and large logic capacity can drive multiple display pipelines, scalers, and color-space converters in parallel. The 624 user I/O can connect to HDMI 2.0, DisplayPort 1.4, and SDI interfaces simultaneously, while the transceiver array handles SDI rates beyond 12 Gbps. Variable-precision DSP blocks accelerate video scaling and deinterlacing algorithms. Industrial temperature rating suits professional broadcast equipment and digital signage. Quartus Prime provides reference designs for common video pipelines, reducing time-to-prototype. For pure consumer-grade volume production, smaller Arria 10 devices may be more cost-effective.
Recommended
ASIC Prototyping
The 10AX115S3F45I2LG is a strong ASIC prototyping vehicle because 1.15M logic elements and 68.86 Mb embedded memory can absorb multi-million-gate ASIC designs partitioned across one or two FPGAs. Industrial temperature rating suits benchtop and lab-deployed prototype hardware. Designers use Quartus Prime's ASIC prototyping flow and design-partitioning guidance to map RTL into the device. The 1932-ball FCBGA F45 package offers generous connectivity for high-pin-count prototypes. Compared with smaller 10AX066 or 10AX090 devices, the 10AX115 enables larger single-chip prototypes and reduces the need for multi-FPG partitioning.
Recommended
High-Speed Serial Backplane Aggregation
The 10AX115S3F45I2LG fits backplane-aggregation line cards because its transceiver array and large logic capacity support multi-protocol bridging between 10G/40G/100G links. The 624 user I/O can connect to multiple SFP+/QSFP cages and to backplane SERDES channels. Industrial temperature rating suits controlled-environment telecom and datacom equipment. The 20 nm process and integrated hard IP minimize the soft-logic overhead and power of multi-protocol bridges. Designers use Quartus Prime's transceiver toolkit for signal-integrity tuning. For higher-density platforms with multiple 100G ports, two Arria 10 devices may replace one larger but more expensive Stratix 10 part.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S3F45I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S3F45I2SG | 10AX115S3F45E2LG | 10AX115S2F45I2LG | 10AX115S2F45I2SG | 10AX115S3F45E2SG | 10AX115S2F45E2LG | 10AX115S1F45I1SG |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1932-BBGA FCBGA (F45) | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | 3 (S3) | 3 | 3 | 2 | 2 | 3 | 2 | 1 |
| Temperature Grade | Industrial (I2, -40C to +100C) | Industrial (I2) | Extended (E2, -40C to +125C) | Industrial (I2) | Industrial (I2) | Extended (E2) | Extended (E2) | Industrial (I1) |
| RoHS / Lead-Free | Yes (LG) | Yes (SG) | Yes (LG) | Yes (LG) | Yes (SG) | Yes (SG) | Yes (LG) | Yes (SG) |
| Process / Core Voltage | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V |
| Embedded Memory | 68.86 Mb | 68.86 Mb | 68.86 Mb | 68.86 Mb | 68.86 Mb | 68.86 Mb | 68.86 Mb | 68.86 Mb |
| User I/O | 624 | 624 | 624 | 624 | 624 | 624 | 624 | 624 |
Key Differentiators
- Largest Arria 10 GX density (1.15M LE) in 1932-ball FCBGA F45 package (vs 10AX090S3F45I2LG)
- Industrial temperature rating with full transceiver lineup (vs 10AX115S3F45E2LG)
- Speed grade 3 (highest) for maximum performance (vs 10AX115S2F45I2LG)
Design Notes
The 1932-ball FCBGA package dissipates significant power under full transceiver and logic utilization. Estimated: at 0.9 V core and 25-30 W typical application power, a high-performance thermal solution is required. Use Intel's Arria 10 thermal-management guidance: heatsink with thermal interface material, sufficient airflow, and a multi-layer PCB with a thermal-via array under the package. Measure junction temperature with the on-die temperature-sensing diode and apply the ALTIMA/SoC EDS thermal model.
The F45 1932-ball FCBGA requires a high-layer-count PCB (typically 12+ layers) with microvia or via-in-pad construction for the BGA escape. Maintain 100-ohm differential impedance for transceiver channels and 50-ohm single-ended for general-purpose I/O. Match transceiver trace lengths within the tolerance specified in the Arria 10 hardware-design guidelines. Place decoupling capacitors on the bottom side of the PCB directly under the package power balls for best high-frequency performance.
Use Intel's Arria 10 pin connection guidelines for unused pins, voltage references, and configuration pins. Decouple each power rail per the datasheet's recommended capacitor network, including bulk, mid-frequency, and high-frequency ceramic capacitors. Route high-speed transceivers on inner stripline layers with continuous reference planes. Avoid routing over plane splits in the transceiver channels - this is a common source of signal-integrity failures at 28 Gbps line rates.
Estimated: A common pitfall is failing to assign configuration pins (nCONFIG, nSTATUS, CONF_DONE, MSEL) per the datasheet before compiling in Quartus Prime. Another pitfall is assuming the Arria 10 power-up sequence is tolerant - the device requires specific rail sequencing per Intel's power-management guidelines. Verify configuration scheme (AS, PS, JTAG, FPP) matches the design's boot requirements. Always run the Quartus Prime Pin Planner and TimeQuest timing analyzer with the correct speed-grade and temperature-grade constraints before board bring-up.
Compliance Information
Lead-free RoHS-compliant per LG suffix in OPN. Industrial temperature grade (I2). Not AEC-Q100 qualified (FPGAs typically are not). REACH compliance per Intel product page.
