10AX115S2F45I2LG - Arria 10 GX 1150K LE FPGA, 1932-FCBGA | Intel
MPN: 10AX115S2F45I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4380 | $438,000.00 |
| 500 | $4120 | $2,060,000.00 |
| 1,000 | $3895 | $3,895,000.00 |
Drop-in alternatives for 10AX115S2F45I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115S2F45E2LG
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$7100 / Unit
View Datasheet →10AX115S2F45I2SG
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View Datasheet →10AX115S2F45E2SG
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View Datasheet →10AX115N3F45I2LG
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View Datasheet →10AX115S1F45I1SG
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View Datasheet →10AX115S2F45I2LG Maximum Ratings & Electrical Characteristics
| Product Family | Arria 10 GX |
| Family Member | 10AX115 |
| Logic Elements (LE) | 1,150,000 |
| Embedded Memory (bits) | 68,857,856 |
| User I/O Pins | 624 |
| Package | 1932-ball FCBGA (F45) |
| Body Size | 45 mm |
| Speed Grade | 2 |
| Operating Temperature Grade | Industrial (I2) |
| Process Technology | 20 nm TSMC |
| Transceivers | Up to 28.05 Gbps |
| Embedded Hard Processor | Dual ARM Cortex-A9 MPCore |
| DSP Blocks | Variable-precision DSP |
| Memory Type | eMLABs + M20K block RAM |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
10AX115S2F45I2LG 1932-ball fcbga (f45) Pin Configuration Guide
Complete pinout information for 10AX115S2F45I2LG (1932-ball fcbga (f45) package) with 624 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115S2F45I2LG.
Refer to the datasheet for full pin configuration.
Estimated pin count: 624 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S2F45I2LG is suitable for 6 applications: 100G Optical Transport Networking, Radar and Electronic Warfare DSP, High-Speed Test and Measurement Equipment, Broadcast Video Processing (4K/UHD), Data Center Acceleration Cards, Industrial Medical Imaging Systems.
100G Optical Transport Networking
The 10AX115S2F45I2LG fits 100G optical transport line cards because its Arria 10 GX fabric includes transceivers up to 28.05 Gbps, enabling direct interface to CFP/CFP2 ACO modules and DSP backplanes. With 1,150,000 logic elements and 68.86 Mbits of block RAM, the device can implement OTN framer/mapper, FEC (Reed-Solomon/SD-FEC), and MACsec encryption in a single chip. The 624 user I/O pins support wide parallel bus interfaces to network processors and switch ASICs. The S2 speed grade provides headroom for 100G framer timing closure while the I2 industrial temperature grade handles central-office deployments.
Recommended
Radar and Electronic Warfare DSP
The 10AX115S2F45I2LG's variable-precision DSP blocks deliver up to 1.5 TFLOPs of fixed/floating-point throughput, which is essential for phased-array radar beamforming, pulse compression, and Doppler processing. The 1,150,000 logic elements allow wide FFT pipelines (up to 4096 points) to run at radar sample rates, while the 68.86 Mbits of embedded memory store chirp lookup tables and windowing coefficients. Industrial temperature rating supports ground-mobile and shipboard radar platforms, and the 1932-ball FCBGA exposes sufficient I/O for multi-channel ADC/DAC interfaces such as JESD204B/C. The integrated ARM Cortex-A9 cores enable real-time OS-based mode control.
Recommended
High-Speed Test and Measurement Equipment
Test instruments such as protocol analyzers, BERT testers, and high-channel-count oscilloscopes leverage the 10AX115S2F45I2LG's 28.05 Gbps transceivers and large logic fabric to capture and decode multi-lane protocols like PCIe Gen3, USB 3.1 Gen2, and 100 Gigabit Ethernet. The 624 user I/O pins interface to high-speed ADCs and DACs in arbitrary waveform generators and digitizers. With 68.86 Mbits of block RAM, deep acquisition memory is on-chip without external SRAM. The S2 speed grade supports real-time triggering and protocol decoding at full line rate, while industrial temperature rating ensures laboratory and field-test reliability.
Recommended
Broadcast Video Processing (4K/UHD)
The 10AX115S2F45I2LG is well suited to 4K/UHD broadcast video processing, including real-time HEVC encoding assist, multi-stream transcoding, and SDI/HDMI/DisplayPort bridging. The 1,150,000 logic elements and 68.86 Mbits of embedded memory allow multiple 4:2:2 12G-SDI input channels to be de-embedded, processed, and re-embedded within one chip. The 624 I/O pins handle 12G-SDI, HDMI 2.0, and 10GbE IP transport interfaces. The integrated ARM Cortex-A9 cores can run a Linux-based control stack for managing codec parameter sets and stream multiplexing. Industrial temperature grade fits OB van and studio equipment environments.
Recommended
Data Center Acceleration Cards
PCIe Gen3 x8 acceleration cards targeting machine-learning inference, database acceleration, and storage offload use the 10AX115S2F45I2LG to combine high-throughput DSP with the integrated hard PCIe Gen3 controller. The device's 1,150,000 logic elements can map a wide SIMD datapath for batched inference, while 68.86 Mbits of on-chip memory hold activations without external DRAM round-trips. The 28.05 Gbps transceivers enable QSFP28 100G fabric or NVMe-over-Fabric connectivity. With the S2 speed grade, designs achieve timing closure on aggressive pipelined accelerators, and the industrial temperature grade supports dense server-rack airflow.
Recommended
Industrial Medical Imaging Systems
Industrial and medical imaging systems such as ultrasound carts, CT scanner reconstruction blades, and machine-vision inspection rigs benefit from the 10AX115S2F45I2LG's combination of 1,150,000 logic elements, variable-precision DSP, and high I/O count. The device can interface to multi-channel JESD204B ADCs digitizing ultrasound transducer arrays or CT detector banks, performing beamforming and back-projection in real time. The 68.86 Mbits of embedded memory hold 3D voxel volumes for intermediate reconstruction. The integrated ARM Cortex-A9 cores run embedded Linux for user interface and image post-processing. Industrial temperature grade supports hospital and factory floor deployments.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S2F45I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S2F45E2LG | 10AX115S2F45I2SG | 10AX115S2F45E2SG | 10AX115N3F45I2LG | 10AX115S1F45I1SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory (bits) | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 |
| Speed Grade | 2 | 2 | 2 | 2 | 3 | 1 |
| Temperature Grade | Industrial (I2) | Extended (E2) | Industrial (I2) | Extended (E2) | Industrial (I2) | Industrial (I1) |
| User I/O Pins | 624 | 624 | 624 | 624 | 624 | 624 |
| Transceiver Max Rate | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 12.5 Gbps (reduced channel count) | 28.05 Gbps |
| Approx. Unit Price (qty 1) | $4,850 | Similar (extended temp) | Similar (tray variant) | Similar | Typically lower | Typically lower (slower speed grade) |
Key Differentiators
- Highest-logic-density drop-in alternative with identical package and industrial temperature grade (vs 10AX115S2F45E2LG)
- S2 speed grade offers better timing margin than lower-speed 10AX115S1F45I1SG variants (vs 10AX115S1F45I1SG)
- S-variant retains full 28.05 Gbps transceiver count while N3 variant reduces channels (vs 10AX115N3F45I2LG)
Design Notes
The 1932-ball FCBGA F45 package requires a high-density PCB with at least 1 oz copper in signal layers and 2 oz copper in power/ground planes. Use via-in-pad (VIPPO) or dog-bone fanout for escape routing; via-in-pad is recommended for the inner rows to minimize via stub effects on high-speed signals. Follow Intel's Arria 10 PCB design guidelines for stackup recommendations including microstrip and stripline impedance targets for 28 Gbps transceiver channels.
Estimate (based on typical Arria 10 core rails at ~0.9 V and transceiver PLLs at ~1.8 V): a fully utilized 10AX115S2F45I2LG can consume 30-45 W. Decouple each power rail with a mix of 10 uF bulk ceramics, 1 uF mid-frequency ceramics, and 0.1 uF/0.01 uF high-frequency ceramics placed as close to the BGA balls as the breakout allows. The SmartVID interface must be connected to a compatible regulator such as the LTM4677 or EM21xx family; without it, the device defaults to a fixed VID that may over-stress the die.
Estimate (using a typical 5 C/W theta_JB for a 45 mm FCBGA with thermal lid and 100 LFM airflow): at 40 W dissipation the junction-to-ambient rise is roughly 12-15 C above ambient, so a heatsink with thermal interface material is generally required. For industrial temperature deployments above 70 C ambient, design the heatsink for 200 LFM of forced airflow and verify with a thermal camera during bring-up. Junction temperature must not exceed 100 C for the I2 grade.
Do not assume all 28.05 Gbps transceivers can be active simultaneously; refer to the Arria 10 Pin Connection Guidelines for the exact number of usable channels per bank at the S2 speed grade. Configuration pins (MSEL, nIO_PULLUP, VCCPD_SEL) must be tied to the correct voltage per the datasheet, otherwise the device will not enumerate on power-up. Leave JTAG (TCK, TMS, TDI, TDO) accessible for in-system programming and Quartus Prime loading.
Match the 100-ohm differential impedance for each transceiver lane and the 50-ohm single-ended impedance for LVDS/CMOS I/O. Length-match the differential pair within 5 mil for data rates up to 10 Gbps and within 2 mil for 25 Gbps+ channels. Use AC coupling capacitors (0.1 uF) at the FPGA TX pins for transceiver channels. Keep the reference plane continuous beneath high-speed traces to avoid impedance discontinuities.
Compliance Information
RoHS and REACH compliance per Intel's environmental documentation. AEC-Q100 not applicable (automotive IC qualification does not apply to FPGAs; for AEC-Q100 qualified automotive grade, consult Intel's automotive FPGA portfolio).
