10M25SAE144I7G - MAX 10 FPGA 25K LE 144-LQFP | Intel / Altera
MPN: 10M25SAE144I7G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $70.12 | $70.12 |
| 10 | $65.4 | $654.00 |
| 100 | $58.2 | $5,820.00 |
| 500 | $51.75 | $25,875.00 |
| 1,000 | $46.8 | $46,800.00 |
Drop-in alternatives for 10M25SAE144I7G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10M25SAE144C8G
β Drop-Inβ In Stock
$32.4 / Unit
View Datasheet β10M25SAE144A7G
β Drop-Inπ Reference alternative (not in catalog)
10M16SAE144I7G
β Drop-Inπ Reference alternative (not in catalog)
10M40SAE144I7G
β Drop-Inβ In Stock
$57.1 / Unit
View Datasheet β10M50SAE144I7G
β Drop-Inπ Reference alternative (not in catalog)
10M16SAE144C8G
β Drop-Inβ In Stock
$27.01 / Unit
View Datasheet β10M25SAE144I7G Maximum Ratings & Electrical Characteristics
| Family | MAX 10 |
| Logic Elements (LE) | 25,000 |
| Embedded Memory (Bits) | 691,200 |
| User I/O Pins | 101 |
| Package | 144-LQFP Exposed Pad (EQFP, E144) |
| Process Node | 55 nm |
| Speed Grade | I7 (-40C to +100C industrial, fastest) |
| Operating Temperature | -40C to +100C (industrial) |
| Core Voltage | 1.2 V (internal) |
| I/O Voltage Support | 3.0 V / 3.3 V (LVCMOS, LVTTL, LVDS, SSTL) |
| On-chip ADC | 4 channels, 12-bit, 1 MSPS |
| Embedded Multipliers (18x18) | 45 |
| PLLs | 4 |
| Configuration | On-chip dual-configuration flash (instant-on) |
| Mounting Type | Surface Mount (LQFP with EPAD) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10M25SAE144I7G Pin Configuration
| Pin 1 | I/O Bank 1 β User I/O (LVCMOS/LVDS, pin assignment varies by Quartus pin-out file) |
| Pin 2 | I/O Bank 1 β User I/O |
| Pin 3 | I/O Bank 1 β User I/O |
| Pin 4 | I/O Bank 1 β User I/O |
| Pin 5 | I/O Bank 1 β User I/O |
| Pin 6 | I/O Bank 1 β User I/O |
| Pin 7 | VCCIO1 β I/O bank 1 supply (3.0 V or 3.3 V) |
| Pin 8 | I/O Bank 1 β User I/O |
| Pin 9 | I/O Bank 1 β User I/O |
| Pin 10 | I/O Bank 1 β User I/O |
| Pin 11 | I/O Bank 1 β User I/O |
| Pin 12 | I/O Bank 1 β User I/O |
| Pin 13 | GND β Ground |
| Pin 14 | I/O Bank 2 β User I/O |
| Pin 15 | I/O Bank 2 β User I/O |
| Pin 16 | I/O Bank 2 β User I/O |
| Pin 17 | VCCIO2 β I/O bank 2 supply (3.0 V or 3.3 V) |
| Pin 18 | I/O Bank 2 β User I/O |
| Pin 19 | I/O Bank 2 β User I/O |
| Pin 20 | I/O Bank 2 β User I/O |
| Pin 21 | GND β Ground |
| Pin 22 | I/O Bank 2 β User I/O |
| Pin 23 | I/O Bank 2 β User I/O |
| Pin 24 | I/O Bank 2 β User I/O |
| Pin 25 | I/O Bank 2 β User I/O |
| Pin 26 | I/O Bank 2 β User I/O |
| Pin 27 | VCCIO2 β I/O bank 2 supply |
| Pin 28 | I/O Bank 2 β User I/O |
| Pin 29 | I/O Bank 2 β User I/O |
| Pin 30 | I/O Bank 2 β User I/O |
| Pin 31 | I/O Bank 2 β User I/O |
| Pin 32 | GND β Ground |
| Pin 33 | I/O Bank 3 β User I/O |
| Pin 34 | I/O Bank 3 β User I/O |
| Pin 35 | I/O Bank 3 β User I/O |
| Pin 36 | VCCIO3 β I/O bank 3 supply |
| Pin 37 | I/O Bank 3 β User I/O |
| Pin 38 | I/O Bank 3 β User I/O |
| Pin 39 | I/O Bank 3 β User I/O |
| Pin 40 | I/O Bank 3 β User I/O |
| Pin 41 | GND β Ground |
| Pin 42 | I/O Bank 3 β User I/O |
| Pin 43 | I/O Bank 3 β User I/O |
| Pin 44 | I/O Bank 3 β User I/O |
| Pin 45 | VCCIO3 β I/O bank 3 supply |
| Pin 46 | I/O Bank 3 β User I/O |
| Pin 47 | I/O Bank 3 β User I/O |
| Pin 48 | I/O Bank 3 β User I/O |
| Pin 49 | GND β Ground |
| Pin 50 | I/O Bank 4 β User I/O |
| Pin 51 | I/O Bank 4 β User I/O |
| Pin 52 | VCCIO4 β I/O bank 4 supply |
| Pin 53 | I/O Bank 4 β User I/O |
| Pin 54 | I/O Bank 4 β User I/O |
| Pin 55 | I/O Bank 4 β User I/O |
| Pin 56 | I/O Bank 4 β User I/O |
| Pin 57 | GND β Ground |
| Pin 58 | I/O Bank 4 β User I/O |
| Pin 59 | I/O Bank 4 β User I/O |
| Pin 60 | I/O Bank 4 β User I/O |
| Pin 61 | I/O Bank 4 β User I/O |
| Pin 62 | VCCIO4 β I/O bank 4 supply |
| Pin 63 | I/O Bank 4 β User I/O |
| Pin 64 | I/O Bank 4 β User I/O |
| Pin 65 | GND β Ground |
| Pin 66 | I/O Bank 5 β User I/O |
| Pin 67 | I/O Bank 5 β User I/O |
| Pin 68 | VCCIO5 β I/O bank 5 supply |
| Pin 69 | I/O Bank 5 β User I/O |
| Pin 70 | I/O Bank 5 β User I/O |
| Pin 71 | I/O Bank 5 β User I/O |
| Pin 72 | I/O Bank 5 β User I/O |
| Pin 73 | GND β Ground |
| Pin 74 | I/O Bank 5 β User I/O |
| Pin 75 | I/O Bank 5 β User I/O |
| Pin 76 | VCCIO5 β I/O bank 5 supply |
| Pin 77 | I/O Bank 5 β User I/O |
| Pin 78 | I/O Bank 5 β User I/O |
| Pin 79 | I/O Bank 5 β User I/O |
| Pin 80 | I/O Bank 5 β User I/O |
| Pin 81 | GND β Ground |
| Pin 82 | I/O Bank 6 β User I/O |
| Pin 83 | I/O Bank 6 β User I/O |
| Pin 84 | VCCIO6 β I/O bank 6 supply |
| Pin 85 | I/O Bank 6 β User I/O |
| Pin 86 | I/O Bank 6 β User I/O |
| Pin 87 | I/O Bank 6 β User I/O |
| Pin 88 | I/O Bank 6 β User I/O |
| Pin 89 | GND β Ground |
| Pin 90 | I/O Bank 6 β User I/O |
| Pin 91 | I/O Bank 6 β User I/O |
| Pin 92 | I/O Bank 6 β User I/O |
| Pin 93 | VCCIO6 β I/O bank 6 supply |
| Pin 94 | I/O Bank 6 β User I/O |
| Pin 95 | I/O Bank 6 β User I/O |
| Pin 96 | I/O Bank 6 β User I/O |
| Pin 97 | GND β Ground |
| Pin 98 | I/O Bank 7 β User I/O |
| Pin 99 | I/O Bank 7 β User I/O |
| Pin 100 | VCCIO7 β I/O bank 7 supply |
| Pin 101 | I/O Bank 7 β User I/O |
| Pin 102 | I/O Bank 7 β User I/O |
| Pin 103 | I/O Bank 7 β User I/O |
| Pin 104 | I/O Bank 7 β User I/O |
| Pin 105 | GND β Ground |
| Pin 106 | I/O Bank 7 β User I/O |
| Pin 107 | I/O Bank 7 β User I/O |
| Pin 108 | VCCIO7 β I/O bank 7 supply |
| Pin 109 | I/O Bank 7 β User I/O |
| Pin 110 | I/O Bank 7 β User I/O |
| Pin 111 | I/O Bank 7 β User I/O |
| Pin 112 | I/O Bank 7 β User I/O |
| Pin 113 | I/O Bank 8 β User I/O |
| Pin 114 | I/O Bank 8 β User I/O |
| Pin 115 | I/O Bank 8 β User I/O |
| Pin 116 | VCCIO8 β I/O bank 8 supply |
| Pin 117 | I/O Bank 8 β User I/O |
| Pin 118 | I/O Bank 8 β User I/O |
| Pin 119 | GND β Ground |
| Pin 120 | I/O Bank 8 β User I/O |
| Pin 121 | I/O Bank 8 β User I/O |
| Pin 122 | I/O Bank 8 β User I/O |
| Pin 123 | VCCIO8 β I/O bank 8 supply |
| Pin 124 | I/O Bank 8 β User I/O |
| Pin 125 | I/O Bank 8 β User I/O |
| Pin 126 | I/O Bank 8 β User I/O |
| Pin 127 | GND β Ground |
| Pin 128 | TCK β JTAG Test Clock |
| Pin 129 | TMS β JTAG Test Mode Select |
| Pin 130 | TDI β JTAG Test Data In |
| Pin 131 | TDO β JTAG Test Data Out |
| Pin 132 | nCONFIG β Configuration control (active low) |
| Pin 133 | nSTATUS β Configuration status (active low) |
| Pin 134 | CONF_DONE β Configuration done |
| Pin 135 | VCCA β PLL analog supply (1.2 V) |
| Pin 136 | VCCD_PLL β PLL digital supply (1.2 V) |
| Pin 137 | GND β Ground |
| Pin 138 | CLK0 β Dedicated clock input 0 |
| Pin 139 | CLK1 β Dedicated clock input 1 |
| Pin 140 | CLK2 β Dedicated clock input 2 |
| Pin 141 | CLK3 β Dedicated clock input 3 |
| Pin 142 | DEV_OE β Device-wide output enable (active low) |
| Pin 143 | DEV_CLRn β Device-wide clear (active low) |
| Pin 144 | GND β Ground (with EPAD) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10M25SAE144I7G is suitable for 6 applications: Industrial Motor Control & FOC, Machine Vision & Image Pre-Processing, Industrial Protocol Bridging (EtherCAT/Profinet/MODBUS), Video Format Conversion & Display Bridging, Low-Cost ASIC/ASSP Replacement & Glue Logic, Edge IoT Sensor Aggregation & Distributed I/O.
Industrial Motor Control & FOC
The 10M25SAE144I7G is well matched to industrial motor-control designs using field-oriented control (FOC) for BLDC and permanent-magnet motors. Its 45 embedded 18x18 multipliers execute the Park/Clarke transforms and PI controllers required for torque and speed loops, while the four integrated 12-bit 1 MSPS ADCs sample phase currents and DC-bus voltage without external analog ICs. The 25,000 logic elements comfortably host state machines, PWM generation, encoder interfaces, and CAN/RS-485 protocol stacks. Industrial temperature grade (-40C to +100C) and instant-on flash configuration satisfy the deterministic startup required by IEC 61800 safety subsystems.
Recommended
Machine Vision & Image Pre-Processing
For machine-vision front-ends and image-sensor pre-processing pipelines, the 10M25SAE144I7G provides the DSP bandwidth and LVDS I/O bandwidth needed to ingest MIPI/Sub-LVDS/HiSPi sensor data and apply Bayer demosaicing, gamma correction, and histogram equalization. The 45 18x18 multipliers accelerate convolution and Sobel kernels, while 691 Kbits of embedded memory buffers line-scan data. The 101 user I/O of the E144 package expose multiple LVDS pairs for parallel image-sensor interfaces, while on-chip ADCs handle ambient-light sensing and analog gain control for the sensor AFE.
Recommended
Industrial Protocol Bridging (EtherCAT/Profinet/MODBUS)
The 10M25SAE144I7G excels at industrial-protocol gateway and bridge applications where multiple fieldbus standards must be translated in real time. Its 25K logic elements accommodate EtherCAT slave controller state machines, Profinet RT/IRT frame handling, and MODBUS TCP/RTU stacks concurrently. The four on-chip ADCs monitor industrial bus voltages and isolation-barrier health, while the 101 user I/O interface with MII/RGMII PHYs and RS-485 transceivers. Industrial temperature grade and instant-on flash make the part suitable for DIN-rail-mounted controllers requiring deterministic cold-start in -40C factory environments.
Recommended
Video Format Conversion & Display Bridging
The 10M25SAE144I7G handles video format conversion between DVI/HDMI receivers, RGB parallel interfaces, and LVDS display panels. Its 45 embedded 18x18 multipliers execute chroma upsampling and color-space conversion (YUV to RGB), while 691 Kbits of embedded memory buffer line and frame data. The 101 user I/O of the E144 package expose LVDS/Sub-LVDS display channels and parallel RGB, sufficient for 720p to 1080p display panels at 60 Hz. Designers can use the on-chip user flash to store EDID and HDCP-key equivalents for embedded-display applications.
Recommended
Low-Cost ASIC/ASSP Replacement & Glue Logic
The 10M25SAE144I7G is a frequent choice for replacing obsolete ASICs or ASSPs in long-lifecycle industrial and medical products where mask-spin costs are prohibitive. Designers can drop the MAX 10 into a pre-existing LQFP-144 footprint and integrate UART, SPI, I2C, PWM, encoder-counter, watchdog, and custom protocol logic in a single chip, eliminating discrete glue logic that previously consumed board area. The on-chip user flash stores configuration constants and calibration data non-volatilely. Instant-on flash configuration eliminates the boot-time latency of SRAM-based FPGAs.
Recommended
Edge IoT Sensor Aggregation & Distributed I/O
For distributed I/O nodes at the edge of industrial Ethernet networks, the 10M25SAE144I7G aggregates multiple analog and digital sensor inputs (RTDs, thermocouples, discrete 24V inputs, encoder counters) and pre-processes them before forwarding to a central controller. Its four 12-bit ADCs sample analog sensor channels at 1 MSPS, while 101 user I/O interface with digital optocouplers and 24V-to-3.3V level shifters. The on-chip user flash stores calibration coefficients per channel. Industrial temperature grade and instant-on behavior suit remote, unheated industrial enclosures with -40C cold-start requirements.
Recommended
Recommended Products Summary
Engineering reference data for 10M25SAE144I7G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10M25SAE144C8G | 10M25SAE144A7G | 10M16SAE144I7G | 10M40SAE144I7G | 10M50SAE144I7G | 10M16SAE144C8G |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) - same | 144-LQFP Exposed Pad (E144) - same | 144-LQFP Exposed Pad (E144) - same | 144-LQFP Exposed Pad (E144) - same | 144-LQFP Exposed Pad (E144) - same | 144-LQFP Exposed Pad (E144) - same |
| Logic Elements | 25,000 | 25,000 | 25,000 | 16,000 | 40,000 | 50,000 | 16,000 |
| Embedded Memory (bits) | 691,200 | 691,200 | 691,200 | 246,000 | 1,134,000 | 1,638,000 | 246,000 |
| 18x18 Multipliers | 45 | 45 | 45 | 16 | 125 | 144 | 16 |
| Speed Grade | I7 (fastest industrial) | C8 (commercial) | A7 (slowest industrial) | I7 | I7 | I7 | C8 |
| Operating Temperature | -40C to +100C | 0C to +85C | -40C to +100C | -40C to +100C | -40C to +100C | -40C to +100C | 0C to +85C |
| On-chip ADC (12-bit, 1 MSPS) | 4 channels | 4 channels | 4 channels | 2 channels | 4 channels | 4 channels | 2 channels |
| User I/O Pins | 101 | 101 | 101 | 78 | 101 | 101 | 78 |
| Configuration Type | On-chip flash (instant-on) | On-chip flash | On-chip flash | On-chip flash | On-chip flash | On-chip flash | On-chip flash |
Key Differentiators
- I7 fastest speed grade for highest Fmax timing closure (vs 10M25SAE144C8G)
- 25K LE provides density headroom over the 10M16 in same footprint (vs 10M16SAE144I7G)
- Four on-chip 12-bit ADCs eliminate external analog ICs (vs 10M25DCF484I7G (BGA-484))
Design Notes
The 144-LQFP exposed-pad (E144) package dissipates 1-2 W under typical 25K-LE designs with high toggle rates. The exposed pad must be soldered to a continuous ground copper pour of at least 25 mm x 25 mm with thermal vias (0.3 mm pitch, 12+ vias) to a bottom-layer ground plane. Estimated: without the thermal via array, junction-to-ambient thermal resistance (theta_JA) exceeds 30 C/W, causing junction temperature to rise 50-60 C above ambient at 1.5 W dissipation. Reference: Intel MAX 10 Hardware Design Guidelines for thermal recommendations.
For LVDS and Sub-LVDS signaling on the MAX 10 E144, maintain 100 ohm differential impedance on the PCB stripline or microstrip, with intra-pair length matching of 150 mils or better. Place 100 nF decoupling capacitors within 5 mm of every VCCIO pin and one 10 uF bulk capacitor per I/O bank. Reference: Intel MAX 10 High-Speed Design Guidelines chapter on PCB layout.
The MAX 10 E144 requires three supply rails: VCCINT (1.2 V core), VCCIOx (3.0 V or 3.3 V per I/O bank, eight banks), and VCCA/VCCD_PLL (1.2 V PLL analog). VCCA must be filtered with a ferrite bead and decoupled with 10 uF + 100 nF; failure to filter VCCA introduces PLL jitter. Estimated: total quiescent current at 25K LE utilization is 80-200 mA depending on clock frequency; toggle-current at 50 MHz LVCMOS 8 mA per pin. Reference: Intel MAX 10 Power Management User Guide.
Do not assume the 10M25 density grade will fit your design without Quartus Prime compile and utilization estimation first; high-utilization designs (>90% LE, >80% memory) frequently fail timing closure in I7G. Use the 10M40SAE144I7G or 10M50SAE144I7G for design headroom in the same E144 footprint. Also note that the on-chip dual-configuration flash limits design iteration speed; use JTAG-mode prototyping before programming the flash.
Compliance Information
RoHS compliant and lead-free per Intel MAX 10 product declaration. Industrial temperature grade (I7G) supports -40C to +100C operation but is NOT AEC-Q100 qualified - choose AEC-Q100 parts from other families for automotive applications. Conflict-minerals declaration per Intel's standard CMRT filing.