EP1M350B780C6 - 350K Gate Mercury FPGA 780-Pin BGA | Altera
MPN: EP1M350B780C6 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $152 | $15,200.00 |
| 500 | $138.75 | $69,375.00 |
| 1,000 | $125 | $125,000.00 |
EP1M350B780C6 Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that combines logic blocks, programmable interconnect, I/O elements, and embedded memory into a single semiconductor die. FPGAs occupy the upper tier of programmable logic - above CPLDs and SPLDs - and serve as flexible hardware platforms between general-purpose microcontrollers and fixed ASICs. The Mercury family extends this concept by adding dedicated high-speed serial interface circuitry and embedded transceiver blocks optimized for serial backplane and telecom data-path applications.
Key features of the EP1M350B780C6 include 350K typical gates (approximately 200K logic elements + dedicated memory and PLL), embedded array blocks (EABs) for RAM/ROM/dual-port memory functions, multiple phase-locked loops (PLLs) for clock management, and high-speed I/O capable of LVDS/LVTTL signalling. The 780-pin FineLine BGA package exposes roughly 488 user I/O pins with rich pin-swappable I/O standards, allowing dense board layouts while preserving signal integrity. The peak reflow temperature rating of 220 C (per the verified distributor records) makes it compatible with standard lead-free SMT assembly profiles.
Architecture-wise, the Mercury family uses a Lookup Table (LUT) based logic element array combined with row/column interconnect, similar to other Altera APEX/Stratix-family predecessors, but enhanced with embedded transceiver macros and CDR circuitry for serial data rates up to 1.25 Gbps per channel. The -6 speed grade balances logic throughput versus static power, sitting between -7 (faster, more leakage) and -8 (slower) grades in the family ordering.
Typical applications for the EP1M350B780C6 include custom telecom line-card designs, serial backplane aggregation, high-speed protocol bridging (SPI 4.2, UTOPIA, POS-PHY), industrial machine-vision frame grabbers, and high-throughput signal-processing prototypes. Designers also use it in software-defined radio (SDR) front-ends and legacy ASIC-replacement programmes where Altera MAX/Quartus tool flow compatibility matters.
When designing with this device, plan power-rail sequencing carefully - the core, I/O, and PLL supplies each require a known-good ramp profile before I/O tri-state is released. Use Altera's Quartus II or MAX+PLUS II tool flow for fitting, place-and-route, and timing closure; older Mercury designs remain supported in Altera/Intel FPGA legacy tool chains.
This page synthesizes distributor pricing snapshots, same-family pin-compatible Mercury drop-in alternatives, and practical layout notes that complement the manufacturer datasheet rather than duplicate it.
Drop-in alternatives for EP1M350B780C6 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP1M350B780C6 (same form factor and footprint) β differing in Package, Operating Temperature, Family, Manufacturer, Speed Grade.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1M350B780C7
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$92 / Unit
View Datasheet βEP1M350B780C5
β Drop-Inβ In Stock
$92.5 / Unit
View Datasheet βEP1M350B780C8
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1M350B780I6
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$145.5 / Unit
View Datasheet βEP1M350B780C6N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1M350B780C6 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera Corporation (now Intel FPGA) |
| Family | Mercury PLD |
| Device Type | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | 350,000 gates |
| Package | 780-pin FineLine BGA |
| User I/O Pins (approx.) | 488 |
| Speed Grade | -6 |
| I/O Standards | LVTTL, LVCMOS, LVDS (per family datasheet) |
| Embedded Transceivers | High-speed serial transceivers (Mercury family feature) |
| Peak Reflow Temperature | 220 C (per distributor records) |
| Mounting Type | Surface Mount (BGA) |
| Programming Interface | JTAG (IEEE 1149.1) + Altera passive serial/AS modes |
| Tool Flow | Quartus II / MAX+PLUS II (Altera legacy) |
| Datasheet File Size | 869 Kbytes (per Alldatasheet index) |
| Datasheet Page Count | 86 pages (per Alldatasheet index) |
EP1M350B780C6 Pin Configuration
| Pin A1 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin A2 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin A3 | VCCIO β I/O supply voltage (per bank) |
| Pin A4 | GND β Ground reference for I/O bank |
| Pin A5 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin B1 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin B2 | VCCINT β Core supply voltage |
| Pin B3 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin B4 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin B5 | GND β Ground reference for I/O bank |
| Pin C1 | VCCIO β I/O supply voltage (per bank) |
| Pin C2 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin C3 | GND β Ground reference for I/O bank |
| Pin C4 | VCCINT β Core supply voltage |
| Pin C5 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin D1 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin D2 | GND β Ground reference for I/O bank |
| Pin D3 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin D4 | VCCINT β Core supply voltage |
| Pin D5 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin E1 | VCCIO β I/O supply voltage (per bank) |
| Pin E2 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin E3 | VCCINT β Core supply voltage |
| Pin E4 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin E5 | GND β Ground reference for I/O bank |
| Pin F1 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin F2 | I/O β User I/O - bank assignment per Quartus Pin Planner |
| Pin F3 | GND β Ground reference for I/O bank |
| Pin F4 | VCCINT β Core supply voltage |
| Pin F5 | I/O β User I/O - bank assignment per Quartus Pin Planner |
Typical Applications
EP1M350B780C6 is suitable for 6 applications: Telecom Line-Card Aggregation, High-Speed Protocol Bridging, Industrial Machine-Vision Frame Grabber, Software-Defined Radio (SDR) Front-End, Legacy ASIC Replacement, High-Throughput Signal-Processing Prototypes.
Telecom Line-Card Aggregation
The EP1M350B780C6 fits telecom line-card aggregation designs because its Mercury-family architecture integrates high-speed serial transceivers (up to 1.25 Gbps per channel) alongside 350K gates of LUT-based logic fabric. The device handles POS-PHY Level 2 / SPI 4.2 / UTOPIA interfaces commonly used in legacy SONET/SDH and Ethernet-over-SONET line cards. Placed on the line-interface card, the FPGA aggregates multiple lower-speed serial links into a single high-speed trunk while performing framing, scrambling, and pointer-processing operations in hardware. With 488 user I/O pins it can sustain dozens of parallel tributary interfaces without external glue logic. Designers benefit from deterministic timing closure on the embedded PLLs versus software-polling microcontroller approaches.
Recommended
High-Speed Protocol Bridging
The EP1M350B780C6 is well suited as a protocol bridge between SPI 4.2, UTOPIA, PCI, and proprietary backplane interfaces because the 350K-gate Mercury logic fabric supports deep FIFO buffering and parallel datapath operations. In a typical bridge, the FPGA receives packets on one interface, performs rate-matching and protocol translation in embedded EAB-based dual-port RAM, and re-emits them on a different interface with sub-microsecond latency. The 780-pin BGA exposes sufficient I/O to support 32-bit or 64-bit wide datapaths alongside multiple clock domains. Its embedded PLLs provide the multiple frequency synthesis needed when bridging between asynchronous clock domains. Trade-off versus an ASIC: the FPGA delivers NRE-free development but dissipates more power at equivalent throughput.
Recommended
Industrial Machine-Vision Frame Grabber
The EP1M350B780C6 serves industrial machine-vision frame-grabber designs where Camera Link or LVDS-based image sensors stream multi-megapixel frames into the FPGA. The Mercury family's LVDS I/O capability supports Camera Link base/medium/full configurations, while 350K gates provide real-time image preprocessing - Bayer demosaicing, gain/white-balance correction, edge detection - at line rates beyond 80 MHz. The embedded EABs buffer full frames in on-chip dual-port RAM, freeing the host CPU from raw-pixel DMA burden. With 488 user I/Os the FPGA can directly drive a Camera Link connector plus auxiliary GPIO for trigger and strobe signals. Industrial machine builders value the deterministic latency over software-based pipelines.
Recommended
Software-Defined Radio (SDR) Front-End
The EP1M350B780C6 enables SDR front-end designs where digitized IF or baseband signals must be channelized, filtered, and demodulated in programmable hardware. The Mercury family's high-speed serial transceivers accept ADC data at hundreds of megahertz, while the LUT fabric implements digital down-conversion, FIR filtering, and symbol-rate conversion. The 350K-gate capacity supports 64-tap or 128-tap polyphase filter banks that would be impractical in a CPLD. SDR designers appreciate the deterministic timing and the ability to reconfigure the same hardware for different waveforms (GSM, WCDMA, WiMAX) without board respins. Trade-off: the -6 speed grade balances logic throughput against power, making it preferable for thermally constrained embedded chassis.
Recommended
Legacy ASIC Replacement
The EP1M350B780C6 frequently replaces obsolete ASICs in long-lifecycle defence, aerospace, and industrial control systems where the original ASIC is no longer mask-programmable. The 350K-gate Mercury fabric maps directly onto most mid-complexity ASIC netlists via Altera's Quartus II synthesis flow, preserving the original RTL investment. Designers retain the same firmware base while gaining the flexibility of field-programmable logic - useful for late-stage bug fixes or feature additions. With 488 user I/O pins and embedded EAB memory, the FPGA typically matches or exceeds the I/O and memory resources of the original ASIC. The NRND status of the EP1M350B780C6 must be balanced against the long-term supportability benefit versus a board-level migration to Cyclone IV.
Recommended
High-Throughput Signal-Processing Prototypes
The EP1M350B780C6 is widely used in research-lab prototypes for radar, sonar, and medical-imaging signal processing where algorithms evolve faster than ASIC tape-out cycles. The 350K-gate capacity supports FFT, convolver, and matrix-multiply datapaths operating at hundreds of MHz, while the embedded EABs implement windowing buffers and twiddle-factor ROMs. The 780-pin BGA exposes enough I/O to interface directly with high-speed ADCs and DACs, eliminating external bus-driver chips. Researchers value the deterministic timing and the ability to re-spin algorithm revisions in software within hours. Trade-off versus modern Stratix 10 / Agilex devices: the EP1M350B780C6 lacks DSP blocks and modern transceivers, so it suits mid-complexity prototyping rather than bleeding-edge designs.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350B780C6 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350B780C7 | EP1M350B780C5 | EP1M350B780C8 | EP1M350B780I6 | EP1M350B780C6N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 780-pin FineLine BGA | 780-pin FineLine BGA - same | 780-pin FineLine BGA - same | 780-pin FineLine BGA - same | 780-pin FineLine BGA - same | 780-pin FineLine BGA - same |
| Speed Grade | -6 | -7 (faster Fmax) | -5 (slower Fmax, lower leakage) | -8 (slowest, lowest leakage) | -6 (industrial temp) | -6 (lead-free) |
| Typical Gates | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 |
| Operating Temperature | Commercial (0 C to +85 C) | Commercial | Commercial | Commercial | Industrial (-40 C to +100 C) | Commercial |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Tool Flow | Quartus II / MAX+PLUS II | Quartus II / MAX+PLUS II | Quartus II / MAX+PLUS II | Quartus II / MAX+PLUS II | Quartus II / MAX+PLUS II | Quartus II / MAX+PLUS II |
Key Differentiators
- Balanced -6 speed grade (vs EP1M350B780C7)
- Commercial temperature range (vs EP1M350B780I6)
- Mercury-family high-speed transceivers (vs EP1K100FC484-2 (ACEX family))
Design Notes
The EP1M350B780C6 requires multiple separate power rails (VCCINT for core, VCCIO per I/O bank, VCC_PLL for phase-locked loops, and VCC_TX/RX for embedded transceivers). Per Altera Mercury reference designs, sequence the core supply first, then I/O banks, then PLLs; releasing I/O tri-state before VCCINT ramps can cause latch-up. Decouple each rail with 0.1 uF X7R ceramic capacitors placed within 5 mm of the respective BGA balls, plus bulk 47-100 uF tantalum or polymer caps on each supply island. Estimated: total static current at 350K-gate utilization typically runs 0.8-1.2 A on VCCINT plus I/O-dependent current on VCCIO; verify with Quartus PowerPlay early in the design.
The 780-pin FineLine BGA exposes a centre thermal pad array that must be soldered to a copper pour on the PCB for adequate heat removal. Per typical Altera BGA thermal guidance, the EP1M350B780C6 has theta_JA in the 8-12 C/W range when the centre balls are soldered to a 4-layer 1 oz copper PCB. Estimated: at full Mercury utilization the device can dissipate 4-6 W; ensure the chassis airflow or heatsink can absorb this continuous dissipation. For -6 speed grade, the static leakage is moderate - lower than -7 but higher than -8 - so thermal budgeting should target the worst-case commercial operating temperature.
Use 8-layer or 10-layer stack-up with dedicated ground and power planes for the 780-pin BGA footprint. Route differential pairs (LVDS) with 100 ohm differential impedance and matched length tolerance under 150 mil across pairs. Use blind/buried vias or micro-vias under the BGA to fan out signals without crowding the breakout region. For embedded transceiver channels, isolate TX/RX differential pairs with ground-fill keep-outs and stitch the ground plane with via fences every lambda/20. Place the JTAG header within 50 mm of the device to keep programming cables short.
Do not assume that any Mercury-family EP1M350 device is drop-in compatible - some variants change VCCINT requirements or PLL supply topology between speed grades. Verify the specific datasheet revision before substituting -5, -6, -7, or -8 grades. Watch for I/O bank VCCIO compatibility when interfacing to 5 V TTL legacy buses - the Mercury family supports LVTTL but requires level-shifters for true 5 V tolerance. Confirm configuration mode (passive serial vs JTAG vs Altera AS) before board bring-up; a misconfigured MSEL pin sequence will leave the FPGA in an undefined state.
Place configuration flash memory (EPCS4/EPCS16) within 25 mm of the FPGA to minimize configuration-clock skew on the DCLK/ASDO path. Keep JTAG TMS/TCK/TDO/TDI traces impedance-controlled to 50 ohm single-ended. Isolate clock inputs (CLK0..CLK3) from high-speed I/O to reduce jitter injection; use guard traces or GND shields. For embedded transceiver channels, route TX-to-RX on different PCB layers to minimize crosstalk, and keep reference-clock traces away from switching power-supply nodes by at least 5 mm.
Compliance Information
RoHS, lead-free, and halogen-free status are not explicitly stated in the Verified Web Data for EP1M350B780C6. Peak reflow temperature of 220 C is consistent with lead-free SMT profiles, but explicit RoHS compliance and halogen-free declarations are not available in the provided data. AEC-Q100 is not applicable as this is a commercial-grade FPGA. Conflict-minerals compliance is unknown.
