EP1M350B780I6 - Altera Mercury 350 FPGA, BGA-780, -40C/+100C | Altera
MPN: EP1M350B780I6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $248.5 | $2,485.00 |
| 100 | $199.75 | $19,975.00 |
| 500 | $168 | $84,000.00 |
| 1,000 | $145.5 | $145,500.00 |
EP1M350B780I6 Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that combines configurable logic blocks (CLBs), programmable interconnects, and dedicated silicon resources such as block RAM, multipliers/DSP blocks, and high-speed transceivers into a single semiconductor die. Within the broader component taxonomy, FPGAs sit above generic logic ICs and below Application-Specific Integrated Circuits (ASICs), occupying the "hardware-reconfigurable" tier of the digital IC hierarchy. The Altera Mercury family specifically targets high-speed signal processing with embedded multiplier blocks and LVDS-capable I/O, suitable for telecom, video, and DSP pipelines.
Key features of the EP1M350B780I6 include its 780-ball FineLine BGA package providing high I/O density, an industrial-grade operating temperature window of -40C to +100C (denoted by the "I" temperature designator and "6" speed grade), a peak reflow temperature rating of 220C compatible with lead-free SMT assembly, and configuration support through the Altera Enhanced Configuration scheme (multi-bit serial/parallel, JTAG). The part is qualified for surface-mount production with MSL handling per JEDEC J-STD-020.
Mercury-family FPGAs implement a sea-of-LABs architecture with embedded array blocks (EABs) for memory functions and dedicated DSP rows. The configuration controller integrates with Altera's Quartus II design flow, accepting compiled SRAM configuration bitstreams via JTAG, serial, or parallel modes. The on-die flash controller (where present on Mercury variants) enables single-chip, instant-on operation without an external configuration PROM.
Typical applications include high-speed DSP datapaths in telecom baseband cards, video processing and imaging front-ends, industrial control and instrumentation, military/aerospace signal processing subsystems, and prototyping bridges for ASIC emulation. The BGA-780 footprint is well-suited to high-density backplane or line-card layouts where LVDS and parallel I/O bandwidth dominate.
When designing with this device, ensure the PCB accommodates the 1.0 mm or 1.27 mm pitch BGA land pattern with proper microvia stack-up, and observe the 220C peak reflow limit for lead-free profile compliance. Power estimation should be performed early using Quartus II PowerPlay to size decoupling and thermal relief.
This page synthesizes distributor pricing, drop-in alternatives, and design notes not consolidated in the original manufacturer datasheet.
Drop-in alternatives for EP1M350B780I6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP1M350B780I6 (same form factor and footprint) — differing in Package, Family, Speed Grade, Operating Temperature, Peak Reflow Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1M350B780C7
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP1M350B780C6
✅ Drop-In✓ In Stock
$125 / Unit
View Datasheet →EP1M350B780C5
✅ Drop-In✓ In Stock
$92.5 / Unit
View Datasheet →EP1M350B780I6 Maximum Ratings & Electrical Characteristics
| Part Number | EP1M350B780I6 |
| Manufacturer | Altera Corporation (now Intel FPGA) |
| Family | Mercury (EP1M) Programmable Logic Device Family |
| Device Type | Field Programmable Gate Array (FPGA) |
| Package | 780-ball FineLine BGA (B780) |
| Operating Temperature Range | -40C to +100C (Industrial, "I") |
| Speed Grade | 6 |
| Peak Reflow Temperature | 220 C |
| Configuration Technology | SRAM-based, Enhanced Configuration Device compatible |
| Mounting Type | Surface Mount (BGA) |
EP1M350B780I6 780-ball fineline bga (b780) Pin Configuration Guide
Pin configuration for EP1M350B780I6 (780-ball fineline bga (b780) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1M350B780I6.
Refer to the datasheet for full pin configuration.
Typical Applications
EP1M350B780I6 is suitable for 6 applications: High-Speed DSP Telecom Baseband, Video and Imaging Front-End Processing, Industrial Control and Instrumentation, Military and Aerospace Signal Processing, ASIC Emulation and Prototyping, Test and Measurement Equipment.
High-Speed DSP Telecom Baseband
The EP1M350B780I6 fits telecom baseband datapaths through its high-density Mercury logic fabric with embedded array blocks (EABs) and dedicated multiplier rows supporting high-throughput DSP filtering and FFT pipelines. The 780-ball BGA exposes the dense parallel and LVDS-capable I/O required to feed ADC/DAC front-ends at hundreds of MS/s without external bus-multiplexing glue. Industrial temperature grade (-40C to +100C) lets the part survive outdoor base-station thermal envelopes. Designers typically pair it with external SRAM/SDRAM for buffer storage and an Altera Enhanced Configuration device for instant-on system bring-up. Compared with a modern Stratix, the EP1M350 draws noticeably more power per DSP op but offers mature Quartus II IP cores that many telecom teams still rely on.
Recommended
Video and Imaging Front-End Processing
For video and imaging front-ends, the EP1M350B780I6 offers the logic density and parallel I/O bandwidth needed to ingest Camera Link or LVDS video streams and run real-time color-space conversion, scaling, and filtering in fabric. The 780-ball BGA delivers the high pin count required for 24-/32-bit parallel video buses plus control I/O without resorting to external serializers. EAB-based line buffers and embedded multipliers accelerate 2D filter kernels, while the industrial temperature range supports machine-vision cameras deployed on factory floors. Design teams typically use Quartus II video IP (Altera Video Suite) and pair the FPGA with DDR SDRAM for frame buffering. Trade-offs: the EP1M350 is power-hungry versus Cyclone V/10 and lacks hard PCIe/ transceiver blocks, so high-speed serial links require external PHY.
Recommended
Industrial Control and Instrumentation
In industrial control and instrumentation, the EP1M350B780I6 serves as a flexible logic hub that aggregates multiple sensor buses (parallel ADC, encoder, RS-485, LVDS) and implements deterministic control loops in hardware. The -40C to +100C industrial window and 220C reflow rating make it a fit for factory-floor PCBs that must survive wide thermal swings and lead-free SMT lines. The Mercury fabric is rich enough to host soft-CPU cores (Nios II) plus custom register-mapped peripherals, allowing one FPGA to replace a microcontroller plus external glue logic. A robust configuration scheme (Altera Enhanced Configuration) supports field firmware updates through JTAG or serial, easing long-lifecycle maintenance.
Recommended
Military and Aerospace Signal Processing
The EP1M350B780I6 is commonly deployed in legacy military and aerospace signal-processing subsystems where programs are long-running and the original Mercury design IP is already certified. The industrial temperature range covers most ground-vehicle and shelter environments, and the BGA-780 package provides the high I/O count needed for parallel sensor arrays and avionics databuses. Although the family is obsolete and not on the latest QML/QPL lists, many platforms still fly with this part because re-qualifying a new FPGA would require costly DO-254/DO-178 evidence regeneration. Designers protect the configuration bitstream with Altera-supported encryption and pair the FPGA with radiation-tolerant external memory for harsh deployments.
Recommended
ASIC Emulation and Prototyping
Engineering teams use the EP1M350B780I6 as an ASIC emulation vehicle when the target ASIC's gate count and clocking fit within the Mercury's logic and I/O budgets. The BGA-780 footprint supports wide parallel buses that mirror the ASIC pin-out, simplifying the prototype-to-emulation harness. Quartus II provides incremental compile and LogicLock region flows that let RTL designers partition and verify the ASIC design on this FPGA before tape-out. The industrial temperature grade is useful when prototyping automotive or outdoor ASICs that must demonstrate thermal tolerance early. Limitation: the EP1M350 lacks the on-chip transceivers and high-speed SerDes of modern prototyping FPGAs, so very high-speed ASICs require a Stratix/Virtex platform instead.
Recommended
Test and Measurement Equipment
In test and measurement instruments (logic analyzers, protocol exercisers, arbitrary waveform generators), the EP1M350B780I6 provides the parallel I/O and fabric density to implement multiple instrument channels while remaining flexible through firmware updates. The 780-ball BGA lets designers expose many LVDS or single-ended channels plus external memory interfaces, and the industrial temperature window suits production-line test racks. Embedded multipliers and EABs accelerate DSP-style stimulus generation and post-processing. The legacy Mercury toolchain (Quartus II) supports mature IP libraries for common serial protocols (I2C, SPI, UART, JTAG) and parallel buses, accelerating instrument firmware development.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350B780I6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350B780C7 | EP1M350B780C6 | EP1M350B780C5 |
|---|---|---|---|---|
| Package | 780-ball FineLine BGA (B780) | 780-ball FineLine BGA (B780) - same | 780-ball FineLine BGA (B780) - same | 780-ball FineLine BGA (B780) - same |
| Brand | Altera | Altera | Altera | Altera |
| Family | Mercury (EP1M) | Mercury (EP1M) | Mercury (EP1M) | Mercury (EP1M) |
| Operating Temperature Range | -40C to +100C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Speed Grade | 6 | 7 | 6 | 5 |
| Peak Reflow Temperature | 220 C | 220 C | 220 C | 220 C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade in the same Mercury B780 footprint (vs EP1M350B780C7)
- Higher speed grade than the slowest Mercury B780 variant (vs EP1M350B780C5)
- Single-piece traceable supply channel via XAIPART for legacy programs (vs EP1M350B780C6 (open-market independent stock))
Design Notes
The Mercury EP1M350 family is fabricated on a 0.18-micrometer process and dissipates substantially more power per MHz than modern 28 nm or 14 nm FPGAs. Estimated: at typical utilization of 70% logic + 50% EAB and a 100 MHz clock, junction-to-ambient thermal rise on a 4-layer JEDEC JESD51 test board with the 780-ball BGA is on the order of 25-35 C/W. For deployments above 60 C ambient, plan for forced-air cooling or a thermal pad bonded to an internal chassis heat-spreader. Designers should run Quartus II PowerPlay early to size the thermal solution before committing to layout.
The 780-ball FineLine BGA uses a fine 1.0 mm pitch that demands a controlled-impedance stack-up with microvias (laser-drilled or stacked). Per JEDEC JESD22-B111 and IPC-9701, route all signal layers as stripline or microstrip with matched impedance (typically 50 ohm single-ended / 100 ohm differential), and provide a continuous ground reference plane directly beneath the BGA to control return paths. Use dog-bone or via-in-pad escape for inner rows; ensure solder mask-defined (SMD) or non-solder mask-defined (NSMD) pad choice is consistent with the assembly house capability to minimize tombstoning and BGA warpage at the 220 C reflow peak.
Do not assume the EP1M350B780I6 ball map is identical to EP1M120F484I6 or EP1M120B484I6 - those are different packages (484-ball BGA) and require their own PCB layout. Mixing Mercury variants on a single board without verifying ball assignment against the Altera datasheet is the most common cause of bring-up failures. Also confirm whether your build uses SRAM-only configuration (requires external EPCS/EPC configuration device) or Enhanced Configuration (on-die flash) - the wrong configuration mode produces a non-functional board even with a correct PCB. Decouple every VCCINT and VCCIO pin with 0.1 uF + 10 uF per the Altera Pin Connection Guidelines.
Mercury LVDS I/O benefits from 100 ohm differential routing with length matching to within 150 mils (3.8 mm) for clock pairs and within 50 mils (1.3 mm) for source-synchronous data/clock groups to keep skew under one unit interval at 500 Mbps. Place series-matching resistors within 200 mils of the driver pin and keep stubs to the FPGA pin under 100 mils. For parallel buses above 100 MHz, simulate with the Altera IBIS models (provided in the Quartus II library) before committing to board fab.
Compliance Information
Peak reflow temperature of 220 C (per verified distributor data) is consistent with lead-free SMT assembly, but RoHS, REACH, halogen-free, and conflict-mineral compliance statements were not found in the verified web excerpts and are marked unknown. AEC-Q100 is not applicable - this is a programmable logic device, not an automotive-grade IC.
