EP20K200CF672C7ES - APEX-II 200K Gate FPGA, 672-BGA | Intel
MPN: EP20K200CF672C7ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268.5 | $2,685.00 |
| 100 | $245 | $24,500.00 |
| 250 | $232 | $58,000.00 |
| 500 | $220 | $110,000.00 |
EP20K200CF672C7ES Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose logic fabric, interconnect, and I/O can be reconfigured after manufacturing, enabling rapid prototyping and hardware-level parallelism. APEX-II sits between classic gate arrays and high-end SoCs: each device combines Look-Up Table (LUT)-based logic, embedded memory blocks, and a high-speed PLD-style interconnect. Within Intel's (formerly Altera's) product taxonomy, APEX-II belongs to the broader Programmable Logic Device (PLD) category, alongside predecessors like FLEX 10K and successors like Cyclone/Stratix families.
Key features include 8,320 logic elements (LEs), up to 106 Kbits of embedded RAM distributed across embedded system blocks, four Phase-Locked Loops (PLLs) for clock management, and MultiVolt I/O supporting 1.5V/1.8V/2.5V/3.3V interfaces. The 672-ball BGA exposes up to 376 user I/O pins, making the EP20K200CF672C7ES well suited for high-density bus aggregation, memory interfaces, and parallel DSP-style datapaths.
Architecturally, APEX-II uses a row-and-column interconnect with continuous FastTrack channels that deliver predictable timing across the die, allowing designers to push designs to higher clock rates than older FLEX architectures. Each Logic Array Block (LAB) groups 10 LEs and is fed by local and global routing resources, while ESBs can be configured as either dual-port RAM or FIFO buffers.
Typical applications include telecommunications line-card glue logic, industrial motor-control co-processors, parallel DSP pipelines, ASIC prototyping, and high-density bus-bridging interfaces. With 200K gates of usable logic, the device targets medium-complexity designs that exceed CPLD capacity but do not require a full Stratix-class solution.
When designing with this part, note that the 672-ball BGA requires a multi-layer PCB with controlled-impedance routing, via-in-pad or microvia assembly, and Xilinx/Altera (Intel) configuration PROM support. Designers should use the legacy Quartus II programmer for bitstream loading (Max+Plus II is also supported) and verify JTAG chain integrity on every board revision.
Drop-in alternatives for EP20K200CF672C7ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K200CF672C7ES (same form factor and footprint) — differing in Speed Grade, Family, Process Technology, System Gates, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400CF672C7ES
✅ Drop-In✓ In Stock
$152 / Unit
View Datasheet →EP20K1000CF672C7ES
✅ Drop-In✓ In Stock
$89.5 / Unit
View Datasheet →EP20K200CF672C8ES
✅ Drop-In✓ In Stock
$158 / Unit
View Datasheet →EP20K200CF672C9ES
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K600CF672C7ES
✅ Drop-In✓ In Stock
$360 / Unit
View Datasheet →EP20K200CF672C7ES Maximum Ratings & Electrical Characteristics
| Family | APEX-II (EP20K) |
| Logic Elements | 8,320 |
| Typical Gates | 200,000 |
| Embedded RAM (max) | 106,496 bits |
| Number of Logic Array Blocks (LABs) | 832 |
| Maximum User I/O Pins | 376 |
| Number of PLLs | 4 |
| Package | 672-ball FineLine BGA |
| Mounting Type | Surface Mount (BGA) |
| Core Voltage | 1.8 V |
| Operating Temperature | 0 °C to +85 °C (Commercial) |
| Speed Grade | 7 |
| Process Technology | 0.18 µm CMOS |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Packaging | Tray |
EP20K200CF672C7ES 672-ball fineline bga Pin Configuration Guide
Pin configuration for EP20K200CF672C7ES (672-ball fineline bga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K200CF672C7ES.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K200CF672C7ES is suitable for 6 applications: Telecommunications Line-Card Glue Logic, Industrial Motor-Control Co-Processor, Parallel DSP / DSP-Farm Datapath, ASIC Prototyping, High-Density Bus Bridging & Aggregation, Legacy Medical Imaging Back-End.
Telecommunications Line-Card Glue Logic
The EP20K200CF672C7ES integrates 8,320 logic elements and 376 user I/Os in a 672-ball BGA, making it a strong fit for legacy telecom line cards that aggregate low-speed framers, map UTMI/STI traffic, and bridge to a backplane ASIC. With four PLLs and MultiVolt I/O (1.5V/1.8V/2.5V/3.3V), the device consolidates discrete 74-series logic and bridges multiple voltage domains on a single chip, simplifying board layout. Designers can use the 106 Kbits of embedded RAM for short packet FIFOs and elastic buffers. Although the part is obsolete, it remains a drop-in solution for sustaining legacy central-office equipment where redesign is not cost-justified.
Recommended
Industrial Motor-Control Co-Processor
Industrial servo and variable-frequency drives often pair an MCU with a programmable-logic co-processor that handles PWM generation, encoder decoding, and high-speed protection logic. The EP20K200CF672C7ES delivers 8,320 LEs sufficient for 3-phase PWM, Hall-sensor decoding, and EtherCAT-related glue logic, while its 376 I/Os interface directly to industrial 24V signaling via external isolators. The four PLLs generate deterministic, jitter-controlled PWM clocks, and the 1.8V core voltage tolerates warm industrial enclosures at 0–85 °C.
Recommended
Parallel DSP / DSP-Farm Datapath
Mid-complexity DSP systems such as baseband pre-processors, video line buffers, and FIR filter arrays benefit from the APEX-II's LUT-based fabric and dual-port ESBs. The 106 Kbits of embedded RAM is configurable as dual-port memory or small FIFOs, allowing the FPGA to implement systolic FIR / FFT structures at the LEs' full clock speed. With 8,320 LEs available, designers can run 4–8 parallel FIR filters or a 64-point radix-4 FFT datapath. While obsolete, the EP20K200CF672C7ES is sometimes found in sustaining-design defense and instrumentation programs.
Recommended
ASIC Prototyping
Before committing an ASIC to fabrication, designers verify RTL on a large FPGA. The EP20K200CF672C7ES is occasionally found in legacy ASIC-emulation boards, mapping single ASIC blocks to one device. The 672-ball BGA gives 376 user I/Os - enough to expose a large SoC bus plus test headers. Quartus II supports partitioned multi-FPGA prototyping flows. For new programs, designers usually move to Stratix/Cyclone 10 LP or modern emulation platforms because APEX-II parts are obsolete.
Recommended
High-Density Bus Bridging & Aggregation
The device's 376 user I/O pins allow it to aggregate multiple parallel buses (e.g., local SRAM, Flash, LCD, USB, and GPIO) into a single high-speed upstream interface. Its MultiVolt I/O support (1.5V/1.8V/2.5V/3.3V) connects directly to mixed-voltage peripherals without external level translators, reducing board area and BOM cost. In legacy printers, scanners, and industrial HMIs, EP20K200CF672C7ES can serve as a custom north-bridge style aggregator.
Recommended
Legacy Medical Imaging Back-End
Some certified medical imaging systems (ultrasound front-ends, MRI back-end preprocessing) built in the early 2000s were designed around APEX-II FPGAs. The EP20K200CF672C7ES can still be specified in maintenance contracts where re-validation of the entire system would be prohibitively expensive. Its deterministic FastTrack interconnect, predictable timing closure, and 1.8V core remain compatible with the original schematics and timing budgets.
Recommended
Recommended Products Summary
Engineering reference data for EP20K200CF672C7ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400CF672C7ES | EP20K1000CF672C7ES | EP20K200CF672C8ES | EP20K600CF672C7ES |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Logic Elements | 8,320 | 16,640 | 38,400 | 8,320 | ~24,192 |
| Typical Gates | 200,000 | 400,000 | 1,000,000 | 200,000 | 600,000 |
| Embedded RAM | 106,496 bits | 212,992 bits | 540,672 bits | 106,496 bits | ~327,680 bits |
| Speed Grade | 7 | 7 | 7 | 8 | 7 |
| Operating Temperature | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (Commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Mid-density APEX-II with strong I/O count (vs EP20K200CF484I8N)
- Capacity-over-room option to higher density in same package (vs EP20K1000CF672C7ES)
- Multiple speed-grade options for cost/performance tuning (vs EP20K200CF672C9ES)
Design Notes
The 672-ball FineLine BGA requires a high-density PCB with microvia or via-in-pad technology. Designers should use at least 6 PCB layers with dedicated GND and 1.8 V VCCINT planes directly under the device. Use 0.4 mm or 0.5 mm ball pitch with controlled-impedance traces; for DDR/SSTL interfaces impedance must be tuned to 50 ohms ±10%. The exposed balls on the bottom of the BGA demand full-array reflow profiling per J-STD-020 to avoid head-in-pillow defects.
Estimated: at 50% LE utilization with typical toggle rate, VCCINT draws roughly 0.5–1.0 A, and each VCCIO bank draws up to 0.3 A. Designers should budget 4–6 distributed decoupling capacitors (0.1 µF X7R + 10 µF tantalum) around each power ball. A 1.8 V LDO with 1.5 A headroom is recommended; for hot-running designs use a buck regulator followed by an LDO post-regulator. Sequence VCCINT before VCCIO per APEX-II datasheet to avoid in-rush latch-up.
Do not attempt to load a Quartus II Stratix/Cyclone bitstream - the configuration format is incompatible with APEX-II. Use Quartus II v4.x or Max+Plus II baselines. EP20K200CF672C7ES is obsolete; long-term reliability programs should verify Date Code, moisture sensitivity level (MSL3, 168 h floor life), and pre-bake components prior to reflow. JTAG TCK should be kept under 10 MHz for chain integrity.
Compliance Information
Lead-free ES suffix per legacy Altera ordering code; RoHS status should be re-verified from the broker's CoC because APEX-II is obsolete and stock may include both Pb and Pb-free finishes.
