EP20K300EFC672-2N - 300K Gates APEX 20KE FPGA | Intel
MPN: EP20K300EFC672-2N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $84.37 | $84.37 |
| 10 | $78.92 | $789.20 |
| 100 | $72.45 | $7,245.00 |
| 500 | $65.8 | $32,900.00 |
| 1,000 | $59.2 | $59,200.00 |
EP20K300EFC672-2N Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that integrates configurable logic blocks, programmable interconnects, and dedicated hard IP such as memory and I/O serializers on a single die. FPGAs sit in the broader semiconductor hierarchy as application-specific standard products (ASSPs) within the programmable logic family, which itself falls under digital integrated circuits. The APEX 20KE architecture specifically introduced MultiCore system-on-a-programmable-chip (SOPC) integration, combining look-up table (LUT)-based logic, embedded system blocks (ESBs) for memory and product-term logic, and high-speed I/O elements, enabling glue-logic replacement, bus bridging, and full custom datapath implementation on a single chip.
Key features of the EP20K300EFC672-2N include 408 maximum user I/Os compliant with multiple I/O standards, 147,456 bits of distributed SRAM organized across embedded system blocks, four phase-locked loops (PLLs) for clock management, and 1.68 ns propagation delay on internal interconnect. The device also supports in-system programmability via IEEE 1149.1 JTAG and configuration via passive serial, passive parallel, and passive asynchronous modes. With up to 350 MHz internal performance, the part targets high-bandwidth datapath and DSP-style designs.
Typical applications for the EP20K300EFC672-2N include telecommunications line cards, custom DSP pipelines, high-speed bus bridges (PCI to local bus), protocol offload engines, and industrial control systems. The 408 user I/Os and 11,520 logic cells make it well suited to designs requiring broad fan-in and wide parallel datapaths, while the embedded memory blocks support FIFO and dual-port RAM functions commonly used in streaming interfaces.
When designing with this part, note that the APEX 20KE family has been in production for many years and is now considered mature. Designers should plan for long lead times on authorized-stock channels and verify that the Quartus design toolchain version supports this device. Power sequencing must follow Intel guidelines: VCCINT must reach 1.8 V before VCCIO to avoid I/O latch-up, and decoupling requires at least 8 ceramic capacitors within 5 mm of the package perimeter.
This page synthesizes distributor pricing as of 2026-09-08, cross-package equivalents within the APEX 20KE family, and practical design considerations not aggregated on standard distributor product pages.
Drop-in alternatives for EP20K300EFC672-2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K300EFC672-2N (same form factor and footprint) — differing in Operating Temperature, Package, Process Technology, Family, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K300EFC672-1N
✅ Drop-In✓ In Stock
$250 / Unit
View Datasheet →EP20K300EFC672-2
✅ Drop-In✓ In Stock
$58.5 / Unit
View Datasheet →EP20K300EFC672-3N
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K300EFC672-1XN
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K300EFC672-1
✅ Drop-In✓ In Stock
$92.4 / Unit
View Datasheet →EP20K300EFC672-2N Maximum Ratings & Electrical Characteristics
| Series | APEX 20KE |
| Family | APEX 20K (MultiCore) |
| System Gates | 300,000 |
| Logic Elements | 11,520 |
| Embedded Memory (bits) | 147,456 |
| Maximum User I/O | 408 |
| Package | 672-pin FineLine BGA (PBGA672) |
| Core Voltage | 1.8 V |
| Process Technology | 0.18 micron CMOS |
| Internal Frequency (max) | 350 MHz |
| Propagation Delay | 1.68 ns |
| Speed Grade | -2 |
| Operating Temperature | 0 C to +85 C (commercial) |
| Configuration Interface | Passive Serial / Parallel / JTAG (IEEE 1149.1) |
| PLLs | 4 |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
EP20K300EFC672-2N 672-pin fineline bga (pbga672) Pin Configuration Guide
Pin configuration for EP20K300EFC672-2N (672-pin fineline bga (pbga672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K300EFC672-2N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K300EFC672-2N is suitable for 6 applications: Telecommunications Line Card Interface, Custom DSP Datapath Acceleration, PCI-to-Local Bus Bridge, Industrial Control System Logic, High-Speed Protocol Offload Engine, Legacy System Replication and Sparing.
Telecommunications Line Card Interface
The EP20K300EFC672-2N is well-suited to telecom line card interface logic where 408 user I/Os enable direct connection to T1/E1 framers, Utopia/ATM PHYs, and network processors. With 300K system gates and 11,520 logic elements, the device can implement custom cell-mapping and queue-management state machines alongside standard bus interfaces, while the four on-chip PLLs generate multiple frequency domains for backplane SERDES and fabric clocks. The 1.8 V core dissipates roughly 1 to 2 W typical at 350 MHz, simplifying thermal design in a 1U blade. Designers often pair this FPGA with a downstream TI TLK1501 SERDES for gigabit serial links.
Recommended
Custom DSP Datapath Acceleration
The 11,520 logic elements and 147 Kbit embedded SRAM allow the EP20K300EFC672-2N to implement custom DSP datapaths such as FIR filters, FFT pipelines, and correlation engines that exceed DSP-processor throughput. The 350 MHz internal frequency supports up to 350 MSPS for fixed-point MAC operations, while the four PLLs provide multiple phase-aligned clocks for sample-rate conversion. Its 408 user I/Os make parallel bus interfaces to external ADCs/DACs straightforward, and 1.8 V core operation keeps dynamic power within budget for fan-less industrial enclosures.
Recommended
PCI-to-Local Bus Bridge
With 408 user I/Os and 300K gates, the EP20K300EFC672-2N can implement a full PCI 2.2 (33 MHz, 32-bit) target or master bridge to a custom local bus, replacing legacy ASIC bridge chips. The four PLLs generate the 33 MHz PCI clock plus a faster local bus clock up to 350 MHz. Embedded memory blocks serve as target-side prefetch buffers and posted-write FIFOs, while 1.8 V core power consumption is acceptable for hot-swap PCI cards. Drop-in compatibility within the APEX 20KE family allows a -1N speed upgrade without PCB redesign when timing closure is tight.
Recommended
Industrial Control System Logic
Industrial controllers benefit from the EP20K300EFC672-2N's 408 user I/Os to directly drive opto-isolated discrete I/O modules, stepper-motor control, and encoder feedback interfaces without intermediate glue logic. The 0 to 85 C commercial operating range suits factory-floor enclosures, and the 1.8 V core plus mature 0.18 micron process yield long-term supply stability. Industrial designers typically use this FPGA to implement custom motion-control state machines, deterministic communication stacks (e.g., EtherCAT slave), and safety interlocks that must run in parallel to a supervisory microcontroller.
Recommended
High-Speed Protocol Offload Engine
The EP20K300EFC672-2N's 11,520 logic elements are sufficient to offload custom protocols (e.g., proprietary backplane, RapidIO-style, or specialty serial) from a host CPU. The 408 user I/Os accept parallel host bus traffic at up to 350 MHz, while the four PLLs synchronize to external reference clocks with sub-nanosecond jitter. Embedded memory blocks (147 Kbit total) buffer packets in transit. Industrial and defense integrators rely on this FPGA when a standard NIC is unavailable and time-to-market prohibits an ASIC spin.
Recommended
Legacy System Replication and Sparing
Many defense, aerospace, and industrial customers maintain legacy APEX 20KE designs that are still in service. The EP20K300EFC672-2N is commonly stocked as a long-term spare to repair or replicate these systems when the original component fails or becomes damaged. Its drop-in compatibility with other -1N, -2N, and -3N speed grades on the same 672-ball FineLine BGA footprint simplifies sparing logistics, and Intel (via Rochester Electronics) continues to ship original-factory parts for support of these long-lifecycle programs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K300EFC672-2N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K300EFC672-1N | EP20K300EFC672-2 | EP20K300EFC672-3N | EP20K300EFC672-1XN | EP20K300EFC672-1 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-ball FineLine BGA (PBGA672) | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Speed Grade | -2 | -1 (faster) | -2 (same) | -3 (slower) | -1X (enhanced) | -1 (faster) |
| Terminal Finish | Lead-free (Pb-free) | Lead-free | Leaded (SnPb) | Lead-free | Lead-free | Leaded |
| System Gates | 300,000 | 300,000 | 300,000 | 300,000 | 300,000 | 300,000 |
| Logic Elements | 11,520 | 11,520 | 11,520 | 11,520 | 11,520 | 11,520 |
| User I/O | 408 | 408 | 408 | 408 | 408 | 408 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Lead-free (Pb-free) terminal finish (vs EP20K300EFC672-2)
- Balanced -2 speed grade for general-purpose designs (vs EP20K300EFC672-3N)
- Highest-density APEX 20KE FineLine BGA option (vs EP20K300EBC652-2)
Design Notes
Estimated: at typical utilization of 60 percent logic, 50 percent memory, and a 200 MHz global clock, the EP20K300EFC672-2N draws approximately 1.2 to 1.8 W from the 1.8 V VCCINT rail. Power-supply design must hold VCCINT within plus or minus 5 percent (1.71 to 1.89 V) under all load transients. Use a buck regulator with at least 2 A capability and a pi-filter (LC) on the output to suppress switching noise. I/O banks can be supplied independently at 3.3 V, 2.5 V, or 1.8 V; tie unused VCCIO pins to the lowest used rail.
The 672-ball FineLine BGA requires a PCB with at least 4 routing layers and 0.4 mm ball pitch escape. Use microvia (laser-drilled) stack-up for inner-row signals; conventional through-via escape is generally not feasible at this pitch. Decoupling: place one 0.1 microfarat ceramic cap and one 10 microfarat tantalum cap within 5 mm of each VCCINT/GND pair. All VCCIO banks must be decoupled independently. Ground bounce can corrupt LVTTL timing - provide at least 8 low-inductance GND balls per quadrant.
Per the APEX 20KE datasheet, VCCINT must reach its valid 1.8 V rail before VCCIO during power-up to avoid I/O latch-up that can permanently damage the device. Implement power-good sequencing with a dedicated supervisor IC (such as the TPS3808) to gate VCCIO with the VCCINT rail-ready signal. Additionally, do not leave any I/O pin floating - all unused pins should be configured as outputs driving low or as inputs with weak pull-ups via the Quartus pin-planner, otherwise floating inputs draw leakage current and can cause in-rush during configuration.
Route the four dedicated global clock inputs (CLK0 through CLK3) on the PCB inner layer with 50-ohm controlled impedance and length matching within plus or minus 50 ps across all four clocks. Place the configuration memory (typically an EPC16 or EPCS4) within 25 mm of the FPGA to keep the passive-serial DCLK and DATA0 traces short. JTAG chain signals (TCK, TMS, TDI, TDO) must be length-matched to within 25 mm to avoid TAP-controller timing violations; add a 10 kilohm pull-up on TCK and TMS to keep the JTAG state predictable during board reset.
Compliance Information
Lead-free (Pb-free) terminal finish indicated by 'N' suffix per Altera ordering information. AEC-Q100 not applicable - this is a commercial-grade (0 to 85 C) FPGA. Halogen-free status not stated in available data.
