EP20K300EFC672-2 - APEX 20KE FPGA 300K Gates 672-BGA | Intel
MPN: EP20K300EFC672-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $84.37 | $84.37 |
| 10 | $80.5 | $805.00 |
| 100 | $72.1 | $7,210.00 |
| 500 | $65 | $32,500.00 |
| 1,000 | $58.5 | $58,500.00 |
EP20K300EFC672-2 Overview
An FPGA (Field-Programmable Gate Array) is a reprogrammable integrated circuit whose logic fabric is configured by the user after manufacture. The APEX 20KE architecture pioneered MultiCore integration, combining look-up table (LUT) logic, embedded memory (ESB), and a system-on-a-programmable-chip (SOPC) interface into a single device. FPGAs sit at the top of the programmable-logic hierarchy (CPLD -> FPGA -> SoC FPGA) and are the most flexible silicon available for parallel, latency-critical digital signal processing and glue logic.
Key features of the EP20K300EFC672-2 include a maximum internal frequency of 350 MHz, a worst-case pin-to-pin propagation delay of 1.68 ns, and a 32-bit PCI-compliant I/O interface. The device supports in-system programmability via IEEE 1149.1 JTAG and the Altera passive serial/EPC configuration scheme, enabling rapid prototyping and field upgrades. The 672-pin FBGA package is part of the FineLine BGA family designed for high-density surface-mount assembly.
Technical depth: APEX 20KE combines four embedded system blocks (ESBs), each implementing dual-port RAM, ROM, or CAM functions, with a logic array organized as MegaLAB structures. This SoPC integration reduces system chip count by absorbing memory and bus-interface functions that historically required companion ASICs. The 0.22 µm process node was selected for a balance of performance and power at the 1.8 V core rail.
Typical applications include PCI bus interfaces, high-speed digital signal processing, glue-logic aggregation in telecom backplanes, and pre-silicon prototyping of ASIC designs. The 408 user I/Os and 147 Kbit of embedded memory are particularly well matched to 32-bit datapath and protocol-converter implementations.
When designing with this device, use the Altera Quartus II design suite (MAX+PLUS II is the legacy toolchain) and ensure all I/O banks are powered before JTAG configuration begins. The 672-pin FBGA requires X-ray inspection for BGA assembly quality verification.
This page synthesizes distributor pricing, drop-in alternatives from the same APEX 20KE family, and PCB-layout guidance not found in the standalone datasheet, helping engineers evaluate longevity and supply-chain options for legacy designs.
Drop-in alternatives for EP20K300EFC672-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K300EFC672-2 (same form factor and footprint) — differing in Operating Temperature, Package, Family, Process Technology, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K300EFC672-2N
✅ Drop-In✓ In Stock
$59.2 / Unit
View Datasheet →EP20K300EFC672-2X
✅ Drop-In✓ In Stock
$99.5 / Unit
View Datasheet →EP20K300EFC672-2XA
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K300EFC672-1
✅ Drop-In✓ In Stock
$92.4 / Unit
View Datasheet →EP20K300EFC672-1N
✅ Drop-In✓ In Stock
$250 / Unit
View Datasheet →EP20K300EFC672-2 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Series | APEX 20K |
| System Gates | 300,000 |
| Logic Elements | 11,520 |
| Embedded Memory (ESB) | 147,456 bits |
| Maximum User I/O | 408 |
| Maximum Internal Frequency | 350 MHz |
| Propagation Delay (pin-to-pin) | 1.68 ns |
| Logic Family | CMOS |
| Core Process Technology | 0.22 µm |
| Core Supply Voltage | 1.8 V |
| Package | 672-pin FineLine BGA (FBGA) |
| Operating Temperature | 0 °C to 85 °C (commercial) |
| Configuration Interface | Passive Serial / EPC / JTAG (IEEE 1149.1) |
| Programming Tool | Quartus II / MAX+PLUS II |
| Mounting Type | Surface Mount (BGA) |
EP20K300EFC672-2 672-pin fineline bga (fbga) Pin Configuration Guide
Pin configuration for EP20K300EFC672-2 (672-pin fineline bga (fbga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K300EFC672-2.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K300EFC672-2 is suitable for 6 applications: PCI Bus Interface Bridge, Telecom Backplane Glue Logic, Pre-Silicon ASIC Prototyping, High-Speed Image Processing Pipeline, Industrial Motor Control, Legacy Avionics Databus Interface.
PCI Bus Interface Bridge
The EP20K300EFC672-2's 408 user I/Os and 32-bit PCI-compliant I/O standard make it ideal for PCI 2.2 bus bridges and protocol-converter implementations. The 11,520 logic elements comfortably absorb a full PCI target or master core plus custom register logic, while the 147,456 bits of embedded system block (ESB) memory provide dual-port buffers for transaction queuing. The 1.68 ns pin-to-pin propagation delay keeps address decoding inside a single PCI clock at 33 MHz, eliminating wait-state insertion. The APEX 20KE MultiCore architecture also co-locates FIFO buffers and bus-arbiter logic on the same die, eliminating the companion bridge ASIC that legacy designs once required.
Recommended
Telecom Backplane Glue Logic
Aggregation of multiple low-speed control signals onto a single high-speed serial backplane is a classic FPGA use case where the EP20K300EFC672-2 shines. Its 408 user I/Os multiplex dozens of LVCMOS/LVTTL control channels into a serialized uplink, while 147 Kbit of embedded memory holds frame buffers and look-up tables for protocol conversion. The 672-pin FBGA package keeps trace lengths short and matched, which is critical at the 350 MHz internal clock speeds the APEX 20KE fabric can sustain. Engineers commonly pair this device with opto-isolators and RS-485 transceivers to aggregate HDSL, E1/T1, or industrial fieldbus links.
Recommended
Pre-Silicon ASIC Prototyping
ASIC design teams use the EP20K300EFC672-2 to prototype million-gate-class designs before committing to mask sets, because the 11,520 logic elements can map large RTL partitions with predictable timing closure. The Quartus II synthesis flow is mature for the APEX 20KE family, and the 672-FBGA package offers enough I/O bandwidth to break out full 32-bit datapath plus JTAG debug visibility. With worst-case pin-to-pin delays of 1.68 ns, engineers can validate clock-domain crossings and FIFO interfaces before tape-out. Once validation completes, the verified RTL migrates to the target foundry process with minimal rework.
Recommended
High-Speed Image Processing Pipeline
Image-processing front ends require parallel pixel-rate arithmetic that microprocessors cannot deliver, and the EP20K300EFC672-2's 11,520 logic elements are well suited for parallel convolution kernels, color-space converters, and histogram engines. The 147 Kbit of dual-port embedded system block (ESB) memory acts as line buffers, supporting pipelined access without external SRAM. With 408 user I/Os the device can ingest wide parallel sensor buses or serialized Camera Link data and emit processed video to a downstream encoder. The 350 MHz internal clock rating keeps arithmetic pipelines well above typical 65 MHz pixel rates.
Recommended
Industrial Motor Control
Multi-axis servo and stepper motor controllers rely on deterministic, high-resolution PWM generation that the EP20K300EFC672-2 delivers through fine-grained logic. The 408 user I/Os interface directly to quadrature encoders, Hall-effect sensors, gate drivers, and absolute-position feedback devices without external multiplexer ICs. The APEX 20KE MultiCore architecture integrates PWM timers, current-loop DSP blocks, and CAN-bus controllers on a single die, reducing board area and BOM. Industrial temperature variants (the -X suffix) of this same package operate from -40 °C to +100 °C for factory-floor deployments.
Recommended
Legacy Avionics Databus Interface
The APEX 20KE family has been designed into MIL-STD-1553 and ARINC 429 databus interface cards for both commercial and military avionics, and the EP20K300EFC672-2's 408 user I/Os simultaneously interface to multiple redundant databus channels plus a host processor. The 11,520 logic elements implement Manchester encoders/decoders, parity engines, and command word filtering entirely in programmable logic. The -X extended-temperature grade operates across the avionics thermal envelope, and the 672-FBGA package withstands vibration profiles compatible with DO-160 testing. Most fielded avionics programs retain the APEX 20KE for lifecycle support reasons.
Recommended
Recommended Products Summary
Engineering reference data for EP20K300EFC672-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K300EFC672-2N | EP20K300EFC672-2X | EP20K300EFC672-2XA | EP20K300EFC672-1 | EP20K300EFC672-1N |
|---|---|---|---|---|---|---|
| Package | 672-FBGA | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Speed Grade | -2 | -2 (same) | -2 (same) | -2 (same) | -1 (slower) | -1 (slower) |
| Operating Temperature | 0 °C to 85 °C commercial | 0 °C to 85 °C commercial | Extended industrial range | Extended industrial range | 0 °C to 85 °C commercial | 0 °C to 85 °C commercial |
| Lead-Free / RoHS | Not specified | Lead-free RoHS compliant | Standard (verify suffix) | Lead-free RoHS compliant | Standard | Lead-free RoHS compliant |
| System Gates | 300,000 | 300,000 | 300,000 | 300,000 | 300,000 | 300,000 |
| Logic Elements | 11,520 | 11,520 | 11,520 | 11,520 | 11,520 | 11,520 |
| Embedded Memory | 147,456 bits | 147,456 bits | 147,456 bits | 147,456 bits | 147,456 bits | 147,456 bits |
| User I/Os | 408 | 408 | 408 | 408 | 408 | 408 |
Key Differentiators
- Lead-free RoHS-compliant drop-in (vs EP20K300EFC672-2N)
- Same pinout, extended temperature (vs EP20K300EFC672-2X)
- Higher speed grade in same package (vs EP20K300EFC672-1)
Design Notes
Estimated: At maximum toggle activity the APEX 20KE 300K-gate die dissipates approximately 2 to 3 W. With the 672-FBGA thermal resistance of roughly 15 °C/W (junction to ambient, still air), the junction temperature rise above 25 °C ambient stays below 45 °C, leaving comfortable margin against the 85 °C commercial limit. Provide at least four thermal vias in the PCB land pattern under the central die flag and route a solid ground pour on the top layer for heat spreading.
The 672-FBGA package has 1.0 mm ball pitch, which requires laser-drilled microvia PCB technology or high-density sequential lamination for fan-out. Place all decoupling capacitors within 2 mm of their respective power and ground balls, using 0.1 µF X7R ceramics for every VCCIO/VCCINT pair and bulk 22 µF tantalums on each supply rail. Match all high-speed differential pairs to within 0.13 mm tolerance and use ground-co-planar waveguides for signals above 100 MHz to control impedance at 50 Ω single-ended or 100 Ω differential.
Do not assume the EP20K300EFC672-2 and EP20K300EBC652-2 are interchangeable; the EFC suffix exposes 408 user I/Os in a 672-FBGA package, while the EBC suffix is a 652-ball BGA with a different ball map. Mixing the two will silently remap I/O banks. Also note that the APEX 20KE is supported only by legacy Quartus II versions (13.0 or earlier) - newer Quartus Prime releases do not target this family.
Compliance Information
RoHS/lead-free status depends on suffix: -2N and -2XA variants are lead-free RoHS-compliant per Altera suffix convention; base -2 and -X may be standard SnPb finish. Verified Web Data did not provide explicit compliance certificates - flagged unknown where not stated.
