EP20K300EFC672-1 - APEX 20KE FPGA 300K Gates 672-BGA | Altera
MPN: EP20K300EFC672-1 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118.75 | $11,875.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92.4 | $92,400.00 |
EP20K300EFC672-1 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit whose logic function is defined after manufacturing by the end user. APEX 20KE belongs to the PLD (programmable logic device) hierarchy: PLD -> CPLD/FPGA -> SRAM-based FPGA -> APEX 20K family -> APEX 20KE (enhanced). The 'E' suffix denotes enhanced ESB memory and additional I/O standards, while the 672-BGA package maximizes pin density for high-bandwidth designs.
Key features include 11,520 logic elements, 147,456 bits of embedded RAM distributed across ESBs, and 1.68 ns propagation delay supporting internal frequencies up to 160 MHz (some sources cite 400 MHz maximum performance grade). The device supports LVCMOS, LVTTL, PCI, GTL+, SSTL-2/3, and LVDS I/O standards via dedicated True-LVDS circuitry, and provides four dedicated fast PLL-style clock inputs. Hot-socketing support enables live insertion into backplane systems.
The MultiCore architecture combines fine-grained LUTs for combinatorial logic with coarse-grained ESBs that can each be configured as dual-port RAM, FIFO, ROM, or CAM. This hybrid structure is optimized for datapath and memory-intensive designs such as telecommunications bridges, ATM switches, and protocol converters. The 672-pin FineLine BGA also enables high-speed SERDES-like parallel interfaces and multiple LVDS channels.
Typical applications for EP20K300EFC672-1 include telecommunications infrastructure (SONET/SDH framers, ATM switching fabrics), data communication routers and bridges, high-speed DSP preprocessing, and industrial control systems with embedded processor cores. The combination of abundant I/O and embedded memory makes it well-suited for system-on-a-programmable-chip (SOPC) integration.
When designing with the EP20K300EFC672-1, engineers should note its EOL status: the APEX 20KE family is obsolete and Intel/Altera recommends Cyclone or newer device families for new designs. Decoupling requires at least 8 bulk and 32 high-frequency ceramic capacitors distributed around the BGA perimeter.
This page synthesizes current distributor inventory, drop-in same-family alternatives, and BGA-layout design notes not collected in a single place in the original Altera datasheet.
Drop-in alternatives for EP20K300EFC672-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K300EFC672-1 (same form factor and footprint) — differing in Operating Temperature, Package, Family, Process Technology, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K300EFC672-2
✅ Drop-In✓ In Stock
$58.5 / Unit
View Datasheet →EP20K300EFC672-3
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K300EFC672-1N
✅ Drop-In✓ In Stock
$250 / Unit
View Datasheet →EP20K300EFC672-1X
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K300EBC652-1
✅ Drop-In✓ In Stock
$215 / Unit
View Datasheet →EP20K300EBC652-1X
✅ Drop-In✓ In Stock
$615.8 / Unit
View Datasheet →EP20K300EFC672-1 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Product Type | FPGA (Field-Programmable Gate Array) |
| System Gates | 300,000 |
| Logic Elements | 11,520 |
| Embedded RAM Bits | 147,456 |
| User I/O | 408 |
| Package | 672-ball FineLine BGA |
| Process Technology | 0.22 um CMOS |
| Core Supply Voltage | 1.8 V (1.71 V min, 1.89 V max) |
| Propagation Delay | 1.68 ns |
| Internal Frequency | 160 MHz (max performance grade up to 400 MHz) |
| Operating Temperature | 0 C to 85 C (commercial) |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, GTL+, SSTL-2/3, LVDS |
| Architecture | MultiCore (LUT + ESB) |
| Mounting Type | Surface Mount (BGA) |
| Logic Family | CMOS, SRAM-based |
| RoHS Status | unknown |
EP20K300EFC672-1 Pin Configuration
| Pin 1 | I/O — User I/O (per datasheet pin table) |
| Pin 168 | I/O — User I/O (per datasheet pin table) |
| Pin 336 | I/O — User I/O (per datasheet pin table) |
| Pin 504 | I/O — User I/O (per datasheet pin table) |
| Pin 672 | I/O — User I/O (per datasheet pin table) |
Typical Applications
EP20K300EFC672-1 is suitable for 6 applications: Telecommunications Switching Fabric, Industrial Protocol Conversion Bridge, DSP Preprocessing Pipeline, Legacy System-on-Programmable-Chip (SOPC), High-Speed Data Acquisition Backplane, Networking Router/Bridge Glue Logic.
Telecommunications Switching Fabric
The EP20K300EFC672-1's 408 user I/O pins and 147,456 bits of embedded RAM (via ESBs) make it well-suited for legacy telecom switching applications. Its 1.8 V core supply and 1.68 ns propagation delay support SONET/SDH framer implementations and ATM cell switching up to 160 MHz internal frequency. The MultiCore architecture combines fine-grained LUTs for control logic with ESB blocks for cell-buffer memory, enabling single-chip integration of framer plus switching fabric. Unlike a generic CPLD, this FPGA provides true parallel datapath processing for OC-3/OC-12 line-card designs, though engineers should note the part is obsolete and consider Cyclone IV GX for new designs.
Recommended
Industrial Protocol Conversion Bridge
With 408 I/O supporting LVCMOS, LVTTL, PCI, GTL+, SSTL-2/3, and LVDS standards, the EP20K300EFC672-1 can serve as a multi-protocol bridge in industrial automation systems. The 672-FineLine BGA enables simultaneous connection to legacy parallel buses and modern LVDS serial links. Its embedded RAM supports FIFOs for clock-domain crossing between asynchronous industrial protocols such as Profibus, DeviceNet, and RS-485. The 0 to 85 C commercial operating range covers most factory-floor environments. Designers should leverage the MultiCore architecture for protocol-state-machine logic while using ESB blocks for buffer memory.
Recommended
DSP Preprocessing Pipeline
The EP20K300EFC672-1's 11,520 logic elements and 1.68 ns propagation delay enable high-throughput DSP preprocessing at clock rates up to 160 MHz. The MultiCore architecture dedicates LUTs for FIR filter taps and ESB blocks for sample buffering, supporting multi-channel audio or video preprocessing pipelines. LVDS I/O enables direct connection to high-speed ADC/DAC converters without external transceivers. Combined with the 1.8 V core supply and low-cost 672-BGA package, the device is well-positioned for custom radar-signal preprocessing, baseband demodulation, or video pre-filtering in defense and instrumentation applications.
Recommended
Legacy System-on-Programmable-Chip (SOPC)
The APEX 20KE family was Altera's first platform marketed as 'system-on-a-programmable-chip,' integrating embedded RAM and abundant I/O for processor-plus-peripheral designs. The EP20K300EFC672-1 supports a soft processor core (e.g., Nios) with 408 I/O for peripheral interfacing and 147 Kbit of on-chip memory for instruction/data storage. Its 1.8 V supply and 0.22 um process deliver lower dynamic power than older APEX 20K parts. Although obsolete, the device remains useful for sustaining legacy Nios-based SOPC products where design revalidation cost outweighs migration benefit to a modern Cyclone platform.
Recommended
High-Speed Data Acquisition Backplane
With 408 user I/O and dedicated True-LVDS support, the EP20K300EFC672-1 can interface to multiple parallel ADC/DAC channels in high-speed data-acquisition backplanes. The 672-FineLine BGA permits dense signal routing for 16-bit or 18-bit converters sampling at 100+ MSPS, with the MultiCore ESB blocks providing on-chip FIFO for sample buffering. Hot-socketing support enables live insertion into VME or cPCI backplanes. While obsolete for new designs, this device continues to serve in long-lifecycle aerospace and defense acquisition systems where re-qualification cost is prohibitive.
Recommended
Networking Router/Bridge Glue Logic
The EP20K300EFC672-1 can consolidate disparate glue-logic functions in legacy router and bridge designs - replacing dozens of TTL/CMOS buffers, transceivers, and protocol converters. Its 408 I/O accommodate PCI bus interfaces (33 MHz), GTL+ memory buses, and LVDS backplane links within a single device. The 147 Kbit embedded RAM supports packet-queue buffering at line-card aggregation points. The device's JTAG support and in-system programmability enable field upgrades via standard boundary-scan tools. Modern Cyclone IV or Arria II GX FPGAs are recommended for new router designs but require PCB redesign.
Recommended
Recommended Products Summary
Engineering reference data for EP20K300EFC672-1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K300EFC672-2 | EP20K300EFC672-3 | EP20K300EFC672-1N |
|---|---|---|---|---|
| Package | 672-FineLine BGA | 672-FineLine BGA - same | 672-FineLine BGA - same | 672-BBGA - same |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Speed Grade | -1 | -2 | -3 | -1 (lead-free) |
| Logic Elements | 11,520 | 11,520 | 11,520 | 11,520 |
| System Gates | 300,000 | 300,000 | 300,000 | 300,000 |
| Embedded RAM Bits | 147,456 | 147,456 | 147,456 | 147,456 |
| User I/O | 408 | 408 | 408 | 408 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (lead-free variant) |
Key Differentiators
- Speed grade -1 offers best cost/performance balance in APEX 20KE 672-BGA (vs EP20K300EFC672-3)
- Lead-free package option for RoHS-compliant designs (vs EP20K300EFC672-1N)
- Maximum I/O density in the APEX 20KE 672-BGA package family (vs EP20K300EBC652-1 (652-BGA))
Design Notes
The 672-ball FineLine BGA requires a multi-layer PCB (typically 6+ layers) with a continuous ground plane beneath the device and dedicated power planes for VCCINT (1.8 V) and VCCIO (3.3 V or 2.5 V depending on bank). Use microvia-in-pad technology for the BGA breakout to escape the 1.0 mm pitch balls. Altera recommends at least 8 bulk decoupling capacitors (100 uF tantalum) and 32 high-frequency ceramics (0.1 uF and 0.01 uF) distributed around the BGA perimeter to suppress switching transients on the 408 simultaneously-switching outputs.
Do not apply input signals before VCCINT and VCCIO have ramped to their specified levels - the APEX 20KE lacks robust cold-sparing on all I/O banks (hot-socketing is supported only on designated banks). Configure unused I/O pins as outputs driving ground or as inputs with internal weak pull-up to prevent floating-pin oscillation. Configuration via passive serial (PS) mode requires the EPC2 or EPC16 configuration PROM; active serial (AS) mode is not natively supported on APEX 20KE. JTAG 1149.1 boundary-scan is the recommended method for board-level interconnect test.
Estimated: at maximum toggle activity (408 I/O switching at 100 MHz, 1.8 V VCCINT), the EP20K300EFC672-1 dissipates approximately 1.5-2.5 W typical. The 672-FBGA package has a theta_JA of approximately 15-20 C/W with proper thermal via array under the exposed die pad; without thermal vias, junction temperature can exceed 100 C. Recommended thermal management: 9 thermal vias (0.3 mm drill) under the center die pad, connected to an internal ground plane, plus 200 LFM minimum airflow for industrial temperature grade operation.
The LVDS I/O on EP20K300EFC672-1 supports data rates up to 840 Mbps per channel with proper board layout. Maintain 100 ohm differential impedance with matched-length traces (within 150 mil) for each LVDS pair. Place 100 ohm termination resistors within 0.5 inch of the receiver end. Series-staggered resistor values (e.g., 22-33 ohm) at the source may be needed if overshoot exceeds VCCIO. SSTL-2 Class I/II memory interfaces require external VTT termination at the memory end and 25 ohm series damping resistors for reliable operation above 100 MHz.
Compliance Information
Original EP20K300EFC672-1 was introduced in 2001 before widespread RoHS transition; the -1N suffix variant is the lead-free option. No RoHS/REACH compliance information was found in the verified web data; refer to original Altera documentation for definitive status.
