Altera

EP20K60EFC144-2X - 60K APEX-20KE FPGA, 93 I/O, 144-BGA | Altera

MPN: EP20K60EFC144-2X ✗ End of Life

In Stock Ships in 1-3 business days

1.8 V (1.71 V – 1.89 V) Vdss 144-pin FBGA (13x13 mm) Package -2 (faster commercial) Speed

From $42.65 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$62.59	$62.59
10	$58.5	$585.00
100	$53.1	$5,310.00
500	$47.8	$23,900.00
1,000	$42.65	$42,650.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EP20K60EFC144-2X Overview

The Altera (Intel Programmable Solutions Group) EP20K60EFC144-2X is a member of the APEX-20KE family of Field Programmable Gate Arrays (FPGAs) delivering 60,000 typical gates with 2,560 logic elements (LEs) and 32,768 bits of embedded RAM. Housed in a 144-pin FineLine BGA (FBGA) package measuring 13x13 mm, the device exposes 93 user I/Os and is fabricated on a 0.22 µm CMOS process node optimized for 1.8 V core operation. The "FC" package suffix denotes the FBGA form factor, while the trailing "-2X" speed grade corresponds to the faster commercial temperature device in the APEX-20KE performance bin.

An APEX-20KE device is a second-generation APEX (Advanced Programmable Element eXtension) FPGA that combines look-up table (LUT)-based logic elements with embedded MultiCore architecture, integrating Look-Up Table (LUT), Embedded System Block (ESB) memory, and product-term logic blocks on a single die. APEX-20KE sits inside the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based LUT FPGA → APEX family → APEX-20KE sub-family. The "E" suffix indicates the ESB-enhanced variant with up to 32,768 bits of dual-port RAM and CAM support, distinguishing it from the original APEX-20K family.

Key features include 2,560 logic elements, 32,768 RAM bits, four Phase-Locked Loops (PLUs) for clock management, MultiVolt I/O support for interfacing with 1.8 V, 2.5 V, 3.3 V and 5.0 V buses, and on-chip boundary-scan (IEEE 1149.1 JTAG) for prototype bring-up. The architecture supports up to four clock networks with dedicated FastCLK inputs and eight low-skew global signals. ESB blocks provide true dual-port RAM, single-port RAM, ROM, and CAM, enabling high-bandwidth on-chip buffering.

Typical applications include telecommunications line cards, industrial control and automation, custom glue logic bridging microprocessors to peripherals, and legacy system refresh of designs originally captured for APEX-20K. The 144-FBGA package is well suited to space-constrained boards where 93 user I/Os are sufficient for parallel datapaths, custom peripheral bridges, or protocol conversion. Designers retain full Quartus II / MAX+PLUS II tool compatibility and the Mbit Flash configuration support of the broader APEX family.

When laying out the PCB, route the four PLL analog supplies (VCC_PLL) with isolated pours and a ferrite bead; switching noise on VCC_PLL directly degrades jitter performance. Place the 144-FBGA on a minimum 4-layer stack-up with continuous VCC and GND planes directly under the package, and follow the IBIS model for output impedance matching on the 93 user I/Os.

This page synthesizes distributor stock, drop-in alternatives from the APEX-20KE family, and practical design notes not consolidated in the original APEX-20KE datasheet.

Drop-in alternatives for EP20K60EFC144-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K60EFC144-2X (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Family, Process Technology.

EP20K200EFC484-2X

Intel

Operating Temperature: 0 °C to 85 °C

Package: 484-FBGA (23x23 mm)

Speed Grade: -2X