Intel

EP2AGX125EF35I5N - Arria II GX FPGA 118K LE, 6x 3.125G Transceivers | Intel

Name: EP2AGX125EF35I5N - Arria II GX FPGA 118K LE, 6x 3.125G Transceivers | Intel
Brand: Intel
SKU: EP2AGX125EF35I5N
Price: 1390 USD
Availability: InStock

MPN: EP2AGX125EF35I5N ✓ Active

In Stock Ships in 1-3 business days

0.9 V Vdss 1152-ball FC-FBGA, 35 x 35 mm Package I5 (industrial, fastest) Speed 8.4 Mbit (M9K + MLAB) Memory

From $1390 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$1850	$1,850.00
10	$1720	$17,200.00
100	$1595	$159,500.00
500	$1480	$740,000.00
1,000	$1390	$1,390,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP2AGX125EF35I5N Overview

The Intel (formerly Altera) EP2AGX125EF35I5N is a high-density Arria II GX Field-Programmable Gate Array (FPGA) delivering 118,143 logic elements, 452 user I/Os, and up to 6 transceivers operating at 3.125 Gbps, housed in a 1152-ball 35x35 mm flip-chip BGA (FC-FBGA-1152) package. It is fabricated on a low-power 40 nm process node, targets the industrial -40C to +100C temperature range (I5 speed grade), and operates from a 0.9 V core supply with 1.5 V/2.5 V/3.3 V-tolerant I/O banks.

An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit containing programmable logic blocks, interconnect, and I/O cells that can be reconfigured by the designer after manufacturing. FPGAs sit within the broader hierarchy of programmable logic devices (PLD) -> logic ICs -> integrated circuits -> semiconductors, and are distinguished from ASICs by their post-fabrication reconfigurability, making them ideal for prototyping, low-volume production, and designs requiring late-stage hardware changes. The Arria II GX family specifically targets mid-range applications that require embedded transceivers and DSP blocks without the cost of high-end Stratix-class parts.

Key features include 124,100 combinational logic blocks (CLBs) organized as 4,964 LABs, 8.4 Mbits of embedded memory (M9K + MLAB blocks), 252 dedicated 18x18 hardware multipliers for DSP, 6 full-duplex 3.125 Gbps CDR-based transceivers with embedded PCI Express hard IP, and 4 phase-locked loops (PLLs). The transceiver hard IP supports protocols including PCI Express Gen1, Gbps, Serial RapidIO, and Custom Ethernet, eliminating the need for external PHY silicon in many designs.

The Arria II architecture uses an 8-input adaptive logic module (ALM) and multi-track interconnect routing that significantly improves logic utilization versus the older 4-input LUT-based Stratix families. The hard PCI Express Gen1 endpoint block and 6x 3.125 Gbps transceivers are integrated directly into the silicon, reducing BOM count and PCB complexity for serial connectivity.

Typical applications include high-volume broadcast video processing, wireless baseband processing (W-CDMA, LTE PHY), test and measurement equipment with high-speed serial I/O, military radar signal processing, and cost-sensitive industrial imaging pipelines. The I5 speed grade provides the fastest timing closure at the cost of higher power than I3 / I7 grades.

When designing with this device, allocate sufficient PCB area for the 35x35 mm package and follow Altera's recommended decoupling scheme with 1 uF and 0.1 uF capacitors per power pin. Use the Quartus II design software (13.0 or later) for synthesis, place-and-route, and timing analysis.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, plus comparison context against other Arria II GX speed/package variants.

Drop-in alternatives for EP2AGX125EF35I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2AGX125EF35I5N (same form factor and footprint) — differing in Package, Speed Grade, Logic Elements, Embedded Memory, Mounting Type.

EP2AGX125DF25I5G

Altera

Package: 572-BGA, FC-FBGA

Speed Grade: I5

Logic Elements: 118,143