EP2AGX95EF35I5N - Arria II GX FPGA, 95K LEs, 1152-FBGA | Intel
MPN: EP2AGX95EF35I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1685 | $1,685.00 |
| 10 | $1580 | $15,800.00 |
| 50 | $1490 | $74,500.00 |
| 100 | $1410 | $141,000.00 |
| 500 | $1295 | $647,500.00 |
| 1,000 | $1180 | $1,180,000.00 |
EP2AGX95EF35I5N Overview
Arria II GX FPGAs belong to Intel's mid-range programmable logic family, positioned between the low-power Cyclone series and the high-end Stratix series. The Arria II line integrates up to 6.375 Gbps transceivers on-die, eliminating external PHY silicon for many protocols such as PCIe Gen2, Serial RapidIO, Gigabit Ethernet, CPRI/OBSAI, and SDI/HD-SDI/3G-SDI. This integration shrinks BOM cost and PCB area for applications where designers would otherwise need a dedicated transceiver companion chip.
Key features include 6 transceiver channels capable of 6.375 Gbps, up to 12 PCIe Gen2 root-complex or endpoint lanes, 8.265 Mbits total memory (mix of MLAB, M9K, and M144K blocks), dedicated hard IP for DDR3 up to 800 Mbps, and 12 PLLs. The 'I' speed grade targets industrial (-40C to +100C Tj) operation while the '5' speed-bin places it in the mid-tier performance class. Core VCC is 0.9V; I/O and transceiver voltages are independent.
Architecturally, Arria II GX uses logic array blocks (LABs) containing adaptive logic modules (ALMs), each ALM holding an 8-input fracturable look-up table, two dedicated adders, and a shared register chain. Embedded transceivers use a hardened PCS/PMA stack supporting multiple protocol modes, and adaptive equalization/cursor pre-emphasis circuitry preserves signal integrity across backplanes and FR-4 traces. Hard PCIe Gen2 IP and the dedicated memory controller free fabric LUTs for application logic, yielding higher effective utilization than soft-IP solutions.
Typical applications include 3G-SDI broadcast video processing and format conversion, LTE/WiMAX baseband DSP front-ends, defense signal-intelligence and software-defined radio, medical ultrasound beamforming, and PCI Express Gen2 endpoint/root-port cards. Designers also deploy it in test-and-measurement ATE boards where 6 Gbps transceivers serve high-speed digitizer or pattern-generator data paths.
When designing with this device, allocate sufficient decoupling (100 nF + 1 uF + 10 uF per power rail) near the FBGA balls, follow Intel's recommended PCB stack-up (typically 12-layer with 50 ohm controlled-impedance routing), and use the Quartus Prime design suite (with Arria II device support) for synthesis, place-and-route, and timing closure. Verify transceiver channel reach with the IBIS-AMI models provided in the device documentation.
This page synthesizes distributor pricing, drop-in alternatives, application guidance, and design notes that go beyond the bare manufacturer datasheet, helping procurement and engineering teams evaluate EP2AGX95EF35I5N for both new designs and legacy board refresh.
Drop-in alternatives for EP2AGX95EF35I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX95EF35I5N (same form factor and footprint) — differing in Package, Process Technology, Logic Elements, Mounting Type, Embedded Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGX125EF35I5N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2AGX95EF35I5G
✅ Drop-In✓ In Stock
$1080 / Unit
View Datasheet →EP2AGX95EF35I3N
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2AGX95EF35C6N
✅ Drop-In✓ In Stock
$1390 / Unit
View Datasheet →EP2AGX95EF29I5N
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2AGX95EF35I3G
✅ Drop-In✓ In Stock
$280 / Unit
View Datasheet →EP2AGX95EF35I5N Maximum Ratings & Electrical Characteristics
| Device Family | Arria II GX |
| Logic Elements | 95,000 (approx.) |
| Embedded Memory (M9K blocks) | 4,525 Kbits |
| Total Embedded Memory | 8,265 Kbits |
| Embedded 18x18 Multipliers | 891 |
| User I/Os | 452 |
| Transceiver Channels | 6 (up to 6.375 Gbps) |
| PCIe Hard IP | Gen2 x4 capable |
| PLLs | 12 |
| Memory Controllers | Hardened DDR3 SDRAM controller (up to 800 Mbps) |
| Package | 1152-ball FBGA |
| Operating Temperature (Tj) | -40C to +100C (industrial) |
| Core Voltage (VCC) | 0.9 V |
| Speed Grade | 5 (mid-tier) |
| Process Technology | 40 nm TSMC low-power |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead Free | Yes |
EP2AGX95EF35I5N 1152-ball fbga Pin Configuration Guide
Pin configuration for EP2AGX95EF35I5N (1152-ball fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX95EF35I5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX95EF35I5N is suitable for 6 applications: 3G-SDI Broadcast Video Processing, Wireless Baseband DSP (LTE / WiMAX), Software-Defined Radio (SDR) / Signal Intelligence, Medical Ultrasound Beamforming, PCI Express Gen2 Endpoint / Root-Port Cards, Test & Measurement / ATE Instrumentation.
3G-SDI Broadcast Video Processing
The EP2AGX95EF35I5N is well-suited to 3G-SDI broadcast video processing thanks to its on-die transceiver channels supporting up to 6.375 Gbps - sufficient for dual-link 3G-SDI at 2.97 Gbps per link, SMPTE 424M, and 6G/12G SDI over multi-link implementations. The hardened PCS/PMA handles SDI clock-rate conversion and FIFO buffering without consuming LUTs, while the 891 dedicated 18x18 multipliers accelerate chroma upscaling, color-space conversion, and motion-adaptive deinterlacing. In a typical design the FPGA sits between an SDI deserializer (e.g., SDI receiver PHY) and DDR3 frame-buffer memory, using the hardened DDR3 controller for full-HD frame-store while fabric logic implements the video pipeline. The 452 user I/Os let the same device accept multiple SDI streams plus HDMI/DisplayPort outputs for multiviewer applications.
Recommended
Wireless Baseband DSP (LTE / WiMAX)
The EP2AGX95EF35I5N serves as the digital front-end of LTE/WiMAX baseband designs, using its 891 dedicated 18x18 multipliers to deliver ~3.4 GMAC/s of signal-processing bandwidth - enough for 20 MHz LTE PHY channels including FFT/iFFT, channel estimation, and MIMO decoding at 2x2 or 4x4 configurations. The integrated 6.375 Gbps transceivers map cleanly onto CPRI/OBSAI links between the baseband FPGA and remote radio heads, eliminating external PHY silicon. Designers typically pair the device with two banks of DDR3 memory (via the hardened memory controller) for HARQ buffering and LLR storage, plus Ethernet MAC cores for backhaul S1/X2 traffic. Quartus DSP Builder accelerates the FPGA implementation of floating-point-to-fixed-point LTE PHY reference designs.
Recommended
Software-Defined Radio (SDR) / Signal Intelligence
Defense and aerospace engineers deploy the EP2AGX95EF35I5N as a flexible SDR front-end for VHF/UHF/S-band signal-intelligence and electronic-warfare applications. The 6.375 Gbps transceivers support wide-bandwidth digitizer interfaces (e.g., 14-bit ADC at 500 MSPS), while the 891 18x18 multipliers implement digital down-conversion, channelization (polyphase filter bank), and pulse-detection DSP kernels. Hardened PCI Express Gen2 x4 endpoint blocks connect the FPGA to host CPU/GPU for downstream processing. A typical SDR reference design routes RF-to-bit through an external ADC into the FPGA's transceiver channels, performs channelization and demodulation in fabric, and ships data over PCIe to a server for further decoding. The industrial -40C to +100C temperature grade supports field deployment in ruggedized enclosures.
Recommended
Medical Ultrasound Beamforming
The EP2AGX95EF35I5N is a strong fit for portable and mid-tier ultrasound beamforming carts, where its 891 dedicated 18x18 multipliers enable real-time beamformed image reconstruction across 32-64 channels. Each channel requires delay-and-sum weighting at the ultrasound sample rate; the FPGA's hardened multipliers and 8.265 Mbits of embedded memory provide the compute density and coefficient storage needed for mid-range cart systems. The hardened DDR3 controller pairs with external DDR3 to buffer raw RF channel data before beamformed image construction. Transceivers support the LVDS link from multi-channel ADCs, simplifying board layout. Designers also implement Doppler processing, harmonic imaging, and elastography in fabric logic alongside the beamformer.
Recommended
PCI Express Gen2 Endpoint / Root-Port Cards
The EP2AGX95EF35I5N integrates a hardened PCI Express Gen2 IP block supporting up to x4 lanes at 5 Gbps per lane, making it a turnkey engine for PCIe endpoint or root-port cards. The hardened IP eliminates the need for soft PCIe cores, freeing fabric logic for application workloads - high-performance data acquisition, GPU-direct computation, NVMe acceleration, or FPGA-direct RDMA. The 6 on-die transceivers provide PCIe plus auxiliary serial links (e.g., 10 GbE, SATA, USB 3.0 via external PHY), while the 452 user I/Os serve as the card-edge interface. Designers pair the device with board-level DDR3 for buffer memory and standard PCIe edge connectors; Quartus PCIe Gen2 MegaWizard generates the link-layer IP and example designs.
Recommended
Test & Measurement / ATE Instrumentation
The EP2AGX95EF35I5N suits automated test equipment (ATE) digitizers, pattern generators, and protocol analyzers thanks to its 6.375 Gbps transceiver channels - enough for high-speed serial interface testing (PCIe Gen2, SATA III, USB 3.0, XAUI) and multi-channel parallel logic test at 200+ MHz. Designers implement custom test vectors in fabric while the hardened PCIe endpoint delivers results to the host controller at near-line rate. The 891 multipliers accelerate FFT-based spectrum analysis and protocol-level pattern matching, and the 8.265 Mbits of embedded memory store per-channel stimulus buffers. Industrial temperature grade supports bench and chamber testing across -40C to +100C. Reference designs from Intel include PXI-Express digitizer modules and protocol analyzer front-ends.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX95EF35I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX125EF35I5N | EP2AGX95EF35I5G | EP2AGX95EF35I3N | EP2AGX95EF35C6N | EP2AGX95EF29I5N | EP2AGX95EF35I3G |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA (EF35, 35mm) | 1152-FBGA (EF35, 35mm) - same | 1152-FBGA (EF35, 35mm) - same | 1152-FBGA (EF35, 35mm) - same | 1152-FBGA (EF35, 35mm) - same | 1152-FBGA (EF29, 29mm) - smaller body, pin-compatible ball map | 1152-FBGA (EF35, 35mm) - same |
| Logic Elements | ~95K | ~125K (+32%) | ~95K (same die) | ~95K (same die) | ~95K (same die) | ~95K (same die) | ~95K (same die) |
| Embedded 18x18 Multipliers | 891 | 1152 (+29%) | 891 (same) | 891 (same) | 891 (same) | 891 (same) | 891 (same) |
| Embedded Memory | 8,265 Kbits | 10,610 Kbits (+28%) | 8,265 Kbits (same) | 8,265 Kbits (same) | 8,265 Kbits (same) | 8,265 Kbits (same) | 8,265 Kbits (same) |
| User I/Os | 452 | 452 (same) | 452 (same) | 452 (same) | 452 (same) | 372 (-18%) | 452 (same) |
| Transceiver Channels | 6 @ up to 6.375 Gbps | 6 @ up to 6.375 Gbps (same) | 6 @ up to 6.375 Gbps (same) | 6 @ up to 6.375 Gbps (same) | 6 @ up to 6.375 Gbps (same) | 6 @ up to 6.375 Gbps (same) | 6 @ up to 6.375 Gbps (same) |
| Speed Grade | 5 (mid-tier) | 5 (same) | 5 (same) | 3 (faster) | 6 (slower) | 5 (same) | 3 (faster) |
| Temperature Grade | Industrial (-40C to +100C Tj) | Industrial (same) | Industrial (same) | Industrial (same) | Commercial (0C to +85C Tj) | Industrial (same) | Industrial (same) |
Key Differentiators
- Integrated 6.375 Gbps transceivers eliminate external PHY silicon (vs EP2AGX95DF25I5N)
- Most drop-in density upgrade path in 1152-FBGA (vs EP2AGX45DF29I5N)
- Hardened PCIe Gen2 IP eliminates soft-IP overhead (vs Soft PCIe cores on competing FPGAs)
Design Notes
The 1152-FBGA package requires a 12-layer PCB with 50 ohm controlled-impedance routing for high-speed serial links. Follow Intel's recommended PCB stack-up with microstrip or stripline traces for transceivers. Place 100 nF + 1 uF + 10 uF decoupling capacitors within 100 mils of each power pin. Use stitched ground vias around signal vias to maintain return-path continuity for 6 Gbps serial channels.
Estimated: at full fabric utilization with all 6 transceivers active at 6.375 Gbps, total power consumption is approximately 8-10 W. The 35mm x 35mm FBGA package has theta_JA around 12 C/W with adequate PCB thermal vias, giving junction temperature rise of 96-120C above ambient. Provide thermal vias under the central power/ground pad array, and consider a heatsink with low thermal resistance to maintain Tj below +100C in industrial applications.
Transceiver channel placement: per the Arria II GX handbook, place transceiver channels adjacent to the FPGA edge nearest the external connector to minimize PCB trace length. Match length within 25 mils across the differential pair, and keep a continuous ground plane beneath the traces. Avoid routing non-transceiver signals across transceiver pairs to prevent crosstalk. Reference Intel's Transceiver Link Design Guidelines for trace geometry, via stubs, and connector recommendations.
Generate the 0.9V core supply with a high-efficiency DC-DC converter (e.g., LTM4623 or ISL8271M) capable of at least 15A peak current. Use a dedicated LDO for the 2.5V VCCA_PLL supply to minimize jitter on the on-die PLLs. Sequence the 1.5V/1.8V VCCPD supply before VCC core to prevent latch-up during power-up. Verify per-rail current with the PowerPlay early power estimator in Quartus before committing to a power-tree design.
Compliance Information
RoHS compliant per Intel product documentation. Industrial temperature grade -40C to +100C Tj per the 'I' suffix. AEC-Q100 not applicable (FPGA is not an automotive-grade part).
