EP2AGX260FF35C5 - Arria II GX FPGA 260K LE, 612 I/O FCBGA-1152 | Intel / Altera
MPN: EP2AGX260FF35C5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2677.78 | $2,677.78 |
| 10 | $2480 | $24,800.00 |
| 100 | $2300 | $230,000.00 |
| 500 | $2150 | $1,075,000.00 |
| 1,000 | $2000 | $2,000,000.00 |
EP2AGX260FF35C5 Overview
Arria II GX FPGAs are mid-range programmable logic devices (PLDs) that combine high-performance digital signal processing (DSP) blocks with multi-gigabit transceivers (MGTs) for serial connectivity. In the broader component taxonomy they sit under programmable logic -> FPGA -> PLD -> semiconductor, and they are complemented by fixed-function ASICs in cost-down high-volume applications and by microcontrollers in software-driven control tasks. The Arria II family specifically bridges the gap between Cyclone (low-cost) and Stratix (high-performance) families by targeting designs that need transceiver-based serial I/O plus sufficient logic density for parallel DSP and memory-intensive algorithms.
Key features of the EP2AGX260FF35C5 include eight 6.375 Gbps multi-gigabit transceivers (C5 speed grade), embedded transceivers supporting PCIe Gen1/Gen2 and multiple SRIO / Serial RapidIO / 10G Ethernet protocols, hard PCI Express hard IP blocks, dedicated DSP blocks for high-speed arithmetic, programmable logic fabric supporting up to 244,188 equivalent logic elements, 12 Mbit of on-chip block RAM, and the FCBGA-1152 package with exposed thermal lid for efficient thermal dissipation. Operating supply voltages are typically 0.9 V core and 1.1 V / 2.5 V / 3.3 V I/O rails with the C5 commercial temperature grade (0 C to +85 C).
Architecturally, the EP2AGX260FF35C5 uses an SRAM-based lookup-table (LUT) logic fabric with column- and row-based routing, dedicated memory block RAM (M20K) tiles, and variable-precision DSP blocks. Each transceiver channel includes clock-data recovery (CDR), serializer / deserializer (SERDES) hardware, and protocol-aware PCS logic to support industry-standard serial interfaces. The device is configured via JTAG or active/passive serial flash, and design entry uses Quartus II / Quartus Prime software.
Typical applications include high-speed serial interface prototyping cards, PCIe Gen2 endpoint adapters, 10G Ethernet line cards, broadcast video processing, military / aerospace signal processing, and ASIC / ASSP prototyping. The wide transceivers and DSP capability make the device a frequent choice for DSP-heavy FPGA-based mezzanine cards (FMC / VITA-57).
When selecting the EP2AGX260FF35C5, designers should plan for a multi-layer PCB with controlled-impedance transceiver lanes, a robust power distribution network with multiple decoupling caps per rail, and thermal relief through via arrays under the package lid. Quartus Prime design software (with device support for Arria II) is required for synthesis, place-and-route, and bitstream generation.
This page consolidates distributor pricing, same-package drop-in alternatives, and practical design considerations - a synthesis not found in any single manufacturer datasheet, distributor product page, or parametric database.
Drop-in alternatives for EP2AGX260FF35C5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX260FF35C5 (same form factor and footprint) β differing in Speed Grade, Package, Operating Temperature, Mounting Type, Package Code.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX260FF35C5N
β Drop-Inβ In Stock
$1545 / Unit
View Datasheet βEP2AGX260FF35C4N
β Drop-Inβ In Stock
$3125 / Unit
View Datasheet βEP2AGX260FF35C4G
β Drop-Inβ In Stock
$1420 / Unit
View Datasheet βEP2AGX260FF35I5N
β Drop-Inβ In Stock
$1325 / Unit
View Datasheet βEP2AGX260FF35C4
β Drop-Inβ In Stock
$2580 / Unit
View Datasheet βEP2AGX260FF35I5
β Drop-Inβ In Stock
$2400 / Unit
View Datasheet βEP2AGX260FF35C5 Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Device Family | Arria II GX |
| Device Type | FPGA - Field Programmable Gate Array |
| Logic Elements (LE) | 244,188 (approx. 260K LE) |
| Number of LABs | 10,260 |
| Embedded Memory (Bits) | 12,038,144 (approx. 1.5 MByte) |
| Maximum User I/O | 612 |
| Number of Pins | 1152 |
| Package | 1152-BBGA / FCBGA-1152 |
| Number of Transceivers | 8 high-speed transceivers |
| Transceiver Data Rate | Up to 6.375 Gbps (C5 speed grade) |
| Speed Grade | C5 (commercial) |
| Operating Temperature | 0 C to +85 C (commercial) |
| Supply Voltage | 0.9 V core, I/O banks at 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant (per DigiKey listing) |
EP2AGX260FF35C5 1152-bbga / fcbga-1152 Pin Configuration Guide
Pin configuration for EP2AGX260FF35C5 (1152-bbga / fcbga-1152 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX260FF35C5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX260FF35C5 is suitable for 6 applications: PCIe Gen2 Endpoint FPGA Card, 10G Ethernet Network Interface Card, DSP and Software-Defined Radio (SDR) Platform, FPGA-based ASIC and ASSP Prototyping, Broadcast Video Processing and Conversion, Military and Aerospace Signal Processing.
PCIe Gen2 Endpoint FPGA Card
The EP2AGX260FF35C5 is well matched to PCIe Gen2 endpoint adapter cards because it integrates hard PCI Express IP blocks supporting x1/x4/x8 lanes at 5 Gbps, plus 8 multi-gigabit transceivers at 6.375 Gbps in the C5 speed grade - comfortably above the PCIe Gen2 line rate with margin. Placed on a PCIe x8 edge-connector card with a downstream downstream 244K LE fabric for user logic, this device delivers deterministic protocol latency and offloads protocol handling from soft logic. Performance benefit vs a soft PCIe implementation is typically 10x lower latency and complete PCS offload. Designers must route the transceiver lanes as 85 ohm differential with skew-matched length, place AC-coupling capacitors within 200 mils of the BGA balls, and allocate four PCB layers for high-speed signal routing plus solid ground and power planes for the 0.9 V core rail.
Recommended
10G Ethernet Network Interface Card
In 10 Gigabit Ethernet (10 GbE) NIC and switch line cards, the EP2AGX260FF35C5 delivers four to eight 10G-capable transceivers at 6.375 Gbps (XAUI 4x lane mode at 3.125 Gbps each, or 10GBASE-R single-lane at 10.3125 Gbps is not supported, so XAUI is the typical mode for this device family). The 244K LE fabric and 12 Mbit of block RAM enable full L2 switching logic, packet parsing, and statistics counters without external memory bottlenecks. Compared with a software-based CPU design, this FPGA approach achieves 4x throughput and deterministic wire-speed forwarding. The device typically operates between 80-95 C junction under full 10G load, so a thermal lid with via-array heat dissipation on the FCBGA-1152 package is essential, and designers should plan for 0.5-1 cfm per-1 watt power air cooling.
Recommended
DSP and Software-Defined Radio (SDR) Platform
The EP2AGX260FF35C5 functions as a high-performance SDR baseband processor because its 244K LE fabric plus dedicated variable-precision DSP blocks support wideband FFTs, channelization filters, and real-time modulation/demodulation at hundreds of MSPS. Each DSP block can sustain approximately 1.5 GMACs at 18x18-bit precision, and the 12 Mbit block RAM provides intermediate buffer storage for pipelined FFT stages. Versus a discrete GPU or DSP, the FPGA approach achieves 3-10x lower latency for closed-loop signal processing - critical for adaptive null-steering, beamforming, and predistortion. The transceivers sample ADC/DAC data at 6.375 Gbps and feed pre-processed streams to the DSP fabric with minimal jitter. Power dissipation is dominated by DSP block switching activity and can exceed 15 W at 100% utilization, so the FCBGA-1152 lid must include a heatsink with at least 4 C/W thermal resistance.
Recommended
FPGA-based ASIC and ASSP Prototyping
ASIC and ASSP design teams use the EP2AGX260FF35C5 as an RTL validation platform because its 244K LE fabric and abundant block RAM can map multi-million-gate ASIC designs with realistic timing and signal integrity. The 8 multi-gigabit transceivers emulate common ASIC SerDes channels for protocol bring-up, and the 612 user I/O support wide external interfaces including DDR3, USB 3.0, and parallel video. Performance benefit vs simulation is real-time execution with full RTL visibility via SignalTap II logic analyzer - reducing verification turnaround by 5-10x versus pure software simulation. For ASIC prototyping, designers typically instantiate multiple EP2AGX260 FPGAs across a multi-FPGA backplane, partitioning the ASIC netlist with vendor partitioning tools. The 35 mm x 35 mm FCBGA-1152 package is large enough to support prototype routing escapes but requires high-layer-count PCB stackups (8+ layers).
Recommended
Broadcast Video Processing and Conversion
In broadcast video processing cards, the EP2AGX260FF35C5 performs real-time SD/HD/3G-SDI up-/down-conversion, scaling, color space conversion, and overlay mixing. The 244K LE fabric supports multiple parallel video processing pipelines at 3 Gbps SDI data rates, and the multi-gigabit transceivers interface directly to SDI physical-layer chips via BNC connectors. The 12 Mbit block RAM acts as line-buffer memory for cross-format conversion without external SDRAM in single-stream designs. Performance benefit vs a DSP-based design is 3-5x lower processing latency - critical for live broadcast workflows. The 8 transceiver channels also support 12G-SDI by aggregating 4 Gbps across 3 Gbps lanes via gearbox logic. Power dissipation under full multi-stream video load typically reaches 8-12 W, so designers should include a thermal interface material between the FCBGA-1152 lid and an aluminum heatsink with airflow.
Recommended
Military and Aerospace Signal Processing
The Arria II GX family, including the EP2AGX260FF35C5, was widely adopted in military / aerospace signal-processing platforms because it combines high logic density, robust transceiver capability, and resistance to obsolescence risks. In these applications the EP2AGX260FF35C5 typically performs I/Q demodulation, channel coding/decoding, and encryption acceleration for radar, EW, and SATCOM systems. Its 8 transceivers handle multi-band IF/feeder signals up to 6.375 Gbps, and the 244K LE fabric supports wideband DSP pipelines. Reliability benefit vs commercial alternatives is the mature Intel FPGA factory support lifecycle (still in active production as of 2026) and proven aerospace pedigree in DO-254 / MIL-STD-461 systems. Designers should select the I5 industrial temperature variant for harsh thermal environments and follow IPC-9592 power-supply guidelines. PCBs typically use 12+ layers with controlled-impedance transceiver routing and buried vias to maximize signal integrity.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX260FF35C5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX260FF35C5N | EP2AGX260FF35C4N | EP2AGX260FF35C4G | EP2AGX260FF35I5N | EP2AGX260FF35C4 | EP2AGX260FF35I5 |
|---|---|---|---|---|---|---|---|
| Package | FCBGA-1152 | FCBGA-1152 - same | FCBGA-1152 - same | FCBGA-1152 - same | FCBGA-1152 - same | FCBGA-1152 - same | FCBGA-1152 - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 244,188 (260K LE) | 244,188 (260K LE) | 244,188 (260K LE) | 244,188 (260K LE) | 244,188 (260K LE) | 244,188 (260K LE) | 244,188 (260K LE) |
| Speed Grade | C5 (commercial) | C5 | C4 (slower) | C4 (slower) | I5 (industrial, faster per temperature) | C4 (slower) | I5 (industrial) |
| Operating Temperature | 0 C to +85 C (commercial) | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | -40 C to +100 C | 0 C to +85 C | -40 C to +100 C |
| Terminal Finish | Tin-Lead (SnPb) | Lead-free (Pb-free) | Lead-free (Pb-free) | Lead-free (Pb-free) | Lead-free (Pb-free) | Tin-Lead (SnPb) | Tin-Lead (SnPb) |
| User I/O | 612 | 612 | 612 | 612 | 612 | 612 | 612 |
| Transceivers | 8 lanes at up to 6.375 Gbps | 8 lanes at up to 6.375 Gbps | 8 lanes at up to 3.75 Gbps (C4 speed) | 8 lanes at up to 3.75 Gbps (C4 speed) | 8 lanes at up to 6.375 Gbps (industrial) | 8 lanes at up to 3.75 Gbps (C4 speed) | 8 lanes at up to 6.375 Gbps (industrial) |
| Embedded Memory | 12,038,144 bits | 12,038,144 bits | 12,038,144 bits | 12,038,144 bits | 12,038,144 bits | 12,038,144 bits | 12,038,144 bits |
Key Differentiators
- C5 speed grade offers highest transceiver performance in this package (vs EP2AGX260FF35C4N)
- Commercial temperature grade suitable for typical indoor deployments (vs EP2AGX260FF35I5N)
- Maximum logic density in FCBGA-1152 form factor (vs EP2AGX125EF35C5G)
- 8 hard multi-gigabit transceiver channels integrated on-die (vs EP2C70F672C8N)
Design Notes
Estimated: at full transceiver utilization (8 lanes at 6.375 Gbps), 100% DSP block usage, and typical 80 MHz fabric clock, the EP2AGX260FF35C5 consumes approximately 15 W with VCCINT = 0.9 V, plus 1.5-2.5 W on each of the transceiver auxiliary supplies (VCCA, VCCPT, VCCP). Plan a multi-rail power distribution network with at least 6-8 decoupling capacitors (10 uF tantalum + 0.1 uF ceramic + 1 nF ceramic) per 4 mm x 4 mm area of fabric. Use a dedicated switching regulator for VCCINT to limit core voltage ripple to under 30 mV peak-to-peak; a low-noise LDO post-regulator is recommended if PCIe Gen2 jitter margins are tight.
The FCBGA-1152 package uses an exposed thermal lid that must be bonded to a heatsink with thermal interface material (TIM) of at least 1 C/W conductivity. Estimated: junction-to-ambient thermal resistance (theta_JA) without heatsink is approximately 12-15 C/W, meaning 15 W dissipation would result in 200 C junction temperature rise above ambient. At 25 C ambient this exceeds the 100 C commercial junction limit - a heatsink with theta_JA under 4 C/W is required, typically achieved with a 30 mm x 30 mm aluminum extrusion and 200 LFM airflow. Designers should also include 0.5 mm-spaced thermal vias (0.3 mm drill, 0.5 mm pad) under the package BGA land pattern.
Route all 8 multi-gigabit transceiver channels as 100 ohm differential pairs (85 ohm for PCIe lanes) with skew-matched length (intra-pair < 1 mil/mm, inter-pair < 50 mil). Place AC-coupling capacitors within 200 mil of the BGA balls and route the TX/RX pairs symmetrically to avoid common-mode conversion. Use 12+ layer PCB stackup with 4 routing layers, 4 ground planes, and 4 power planes; place high-speed signals between adjacent ground layers. Reference Altera's AN 539: Transceiver Link Design Guidelines for the complete transceiver board-design checklist.
Avoid these common pitfalls when designing with EP2AGX260FF35C5: (1) do not mix voltage references on I/O banks - different banks require separate VCCIO supplies and must be sequenced correctly to prevent latchup; (2) do not skip the POR (power-on-reset) circuit - the FPGA must see a clean ramp on VCCINT with monotonic rise time of 200 us to 100 ms; (3) do not forget to configure unused I/O pins as tri-stated inputs with weak pull-up enabled to minimize power and noise; (4) do not overlook JTAG TCK pull-down requirements (4.7 kohm) when designing the configuration interface.
Compliance Information
RoHS compliance noted per DigiKey listing - however, the EP2AGX260FF35C5 (without N suffix) is tin-lead (SnPb) finished per Partstack specification, so it is NOT lead-free. Choose EP2AGX260FF35C5N or other N-suffix variants for fully lead-free (RoHS) assemblies.
