EP2AGX260FF35C6G - Arria II GX FPGA 244K LE | Intel | 1152-FCBGA
MPN: EP2AGX260FF35C6G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 100 | $1580 | $158,000.00 |
| 500 | $1450 | $725,000.00 |
| 1,000 | $1320 | $1,320,000.00 |
EP2AGX260FF35C6G Overview
An FPGA is a reconfigurable integrated circuit whose logic, memory, and I/O blocks are defined by a configuration bitstream rather than fixed masks. The Arria II GX family sits within Intel's (formerly Altera) mid-range product hierarchy: FPGA -> programmable logic -> PLD -> semiconductor. Compared with CPLDs, FPGAs offer far higher logic density and block-RAM; compared with ASICs, FPGAs provide rapid prototyping and post-silicon field upgrades through partial reconfiguration.
Key features include 8 PLLs for clock management, support for DDR2/DDR3/QDRII+ external memory interfaces, integrated PCI Express hard IP blocks, and transceivers compliant with PCIe Gen1/Gen2, GIGE, XAUI, and Serial RapidIO protocols. Hard DSP blocks accelerate fixed- and floating-point operations, while the Quartus II design suite provides synthesis, place-and-route, and timing closure for the device. The C6 speed grade denotes a mid-tier performance bin optimized for industrial and commercial designs.
The Arria II GX architecture uses a 40 nm process node, delivering sub-watt static power and dynamic power gated through the Quartus PowerPlay tool. Distributed and column-based M20K memory blocks deliver up to 612 embedded multipliers for high-throughput DSP pipelines, while 24 global clock networks support complex multi-clock-domain SoC designs.
Typical applications include wireless baseband processing, high-speed serial bridge and protocol conversion, broadcast video processing, industrial machine vision, and PCI Express endpoint cards. The transceiver count and protocol support also make the part suitable for telecom backhaul aggregation and test-and-measurement instrumentation front ends.
When designing with the EP2AGX260FF35C6G, allocate adequate PCB area for the FCBGA escape routing and a minimum 8-layer stack-up for transceiver signal integrity. Use the Quartus II transceiver toolkit for pre-emphasis and equalization tuning, and verify the JTAG chain against the BSDL file before bringing up prototype boards.
This page synthesizes current distributor pricing, package-matched drop-in alternatives from the same Arria II GX family, and design notes that complement the official datasheet.
Drop-in alternatives for EP2AGX260FF35C6G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX260FF35C6G (same form factor and footprint) β differing in Speed Grade, Package, Operating Temperature, Transceivers, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX260FF35C6
β Drop-Inβ In Stock
$1795 / Unit
View Datasheet βEP2AGX260FF35C5G
β Drop-Inβ In Stock
$1395 / Unit
View Datasheet βEP2AGX260FF35C5
β Drop-Inβ In Stock
$2000 / Unit
View Datasheet βEP2AGX260FF35C5N
β Drop-Inβ In Stock
$1545 / Unit
View Datasheet βEP2AGX260FF35C4G
β Drop-Inβ In Stock
$1420 / Unit
View Datasheet βEP2AGX260FF35C4N
β Drop-Inβ In Stock
$3125 / Unit
View Datasheet βEP2AGX260FF35C4
β Drop-Inβ In Stock
$2580 / Unit
View Datasheet βEP2AGX260FF35C6G Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Logic Elements | 244,188 |
| Embedded Memory | 12,038,144 bits |
| Embedded Multipliers | 612 (18x18) |
| Transceivers | 16 channels |
| Max Transceiver Data Rate | 6.375 Gbps |
| PLLs | 8 |
| Package | 1152-BBGA, FCBGA |
| Speed Grade | C6 |
| Operating Temperature | 0C to +85C (commercial) |
| Mounting Type | Surface Mount |
| Process Node | 40 nm |
| Memory Type | M20K block RAM + distributed MLAB |
| RoHS Status | Compliant |
| Lead Free | Yes |
EP2AGX260FF35C6G Pin Configuration
| Pin A1 | VCC β Core/IO supply voltage |
| Pin A2 | GND β Common ground |
| Pin B1 | IO β User I/O pin |
| Pin B2 | GXB_TXp β Transceiver transmit positive |
| Pin C1 | GXB_TXn β Transceiver transmit negative |
| Pin C2 | GXB_RXp β Transceiver receive positive |
| Pin D1 | GXB_RXn β Transceiver receive negative |
| Pin D2 | REFCLK_p β Transceiver reference clock positive |
| Pin E1 | REFCLK_n β Transceiver reference clock negative |
| Pin E2 | JTAG_TCK β JTAG test clock |
Typical Applications
EP2AGX260FF35C6G is suitable for 7 applications: Wireless Baseband Processing, High-Speed Serial Bridge and Protocol Conversion, Broadcast Video Processing, Industrial Machine Vision, PCI Express Endpoint and Add-In Cards, Test and Measurement Instrumentation, Telecom Backhaul Aggregation.
Wireless Baseband Processing
The EP2AGX260FF35C6G's 244,188 logic elements and 612 18x18 multipliers deliver the DSP throughput required for LTE and 5G NR baseband channel cards. The 16 transceivers at up to 6.375 Gbps interface directly to CPRI/OBSAI links to remote radio heads, eliminating external PHY chips. Designers can map turbo decoders, FFT/iFFT engines, and matrix pre-coding onto dedicated DSP blocks while keeping static power under 1W through Quartus PowerPlay gating. The C6 speed grade supports 245.76 MHz CPRI line rates with comfortable timing margins.
Recommended
High-Speed Serial Bridge and Protocol Conversion
Multi-protocol bridges (PCIe Gen2 to XAUI, Serial RapidIO to Ethernet, or CPRI to fibre) benefit from the 16 integrated transceivers and 8 PLLs of the EP2AGX260FF35C6G. Hard PCIe Gen2 IP blocks accelerate endpoint and root-port designs; XAUI and 10G-KR cores are also supported in Quartus II. With 12 Mbit embedded memory, the device buffers full Ethernet frames on-chip, eliminating external RLDRAM in many converter designs and reducing BOM cost. FCBGA escape supports 100-ohm differential routing on inner stripline layers.
Recommended
Broadcast Video Processing
Broadcast video routers, format converters, and multiviewer cards rely on the EP2AGX260FF35C6G's parallel multiplier density and high-speed transceiver count. The 612 18x18 multipliers accelerate colour-space conversion (YUV to RGB), scaling kernels, and SDI de-embedding/embedding in real time. SDI transceivers connect via the FPGA's general-purpose 3.125 Gbps transceivers, while HDMI 2.0 input/output can be implemented using HDMI IP cores in the programmable fabric. The 1152-ball FCBGA supports the dense I/O needed for SD/HD/3G-SDI parallel buses.
Recommended
Industrial Machine Vision
GigE Vision and CoaXPress frame grabbers use the EP2AGX260FF35C6G's 16 transceivers to host up to four PoE+ GigE ports or one 6.25 Gbps CoaXPress uplink. The 244K-LE fabric preprocesses images with hardware Sobel, FFT, and histogram stages, offloading the host CPU. Embedded M20K memory buffers full 4K frames line-by-line, enabling real-time defect detection on conveyor lines. The commercial 0C to +85C operating range supports factory-floor deployments without derating.
Recommended
PCI Express Endpoint and Add-In Cards
The EP2AGX260FF35C6G includes hard PCI Express Gen2 IP blocks (x1/x4/x8), enabling endpoint add-in cards, RAID controllers, and FPGA co-processor boards. The 16 transceivers support PCIe x8 Gen2 (5 Gbps per lane) plus side-band 10G Ethernet for hybrid cards. Integrated PLLs simplify reference-clock distribution; the FCBGA's low-jitter power/ground assignment supports PCIe link-training margin. Quartus II PCIe IP delivers TLP/DLLP layer, MSI-X interrupt, and Gen3-ready soft logic.
Recommended
Test and Measurement Instrumentation
Modular instruments (PXIe, LXI, AXIe) use the EP2AGX260FF35C6G for ADC/DAC capture and waveform synthesis. The 244K LE handles multi-channel real-time DSP, while 16 transceivers stream data to a host CPU over PCIe Gen2 or 10 GigE. Designers can map FIR, FFT, and decimation stages onto the device's 612 multipliers, achieving GSPS-class effective sample rates. The FCBGA's thermal performance sustains continuous 100% duty-cycle DSP workloads at 85C ambient.
Recommended
Telecom Backhaul Aggregation
Carrier Ethernet aggregation switches and CPRI-to-Ethernet gateways use the EP2AGX260FF35C6G's 16 transceivers to terminate multiple CPRI links and forward Ethernet traffic. The 244K-LE fabric implements QoS, VLAN tagging, and timing-over-packet features (IEEE 1588v2) in software. With 8 PLLs and on-chip M20K memory, the device builds 1588 hardware timestamps at line rate with sub-100 ns accuracy, critical for mobile fronthaul timing requirements.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX260FF35C6G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX260FF35C6 | EP2AGX260FF35C5G | EP2AGX260FF35C5 | EP2AGX260FF35C5N | EP2AGX260FF35C4G | EP2AGX260FF35C4N | EP2AGX260FF35C4 |
|---|---|---|---|---|---|---|---|---|
| Package | 1152-BBGA FCBGA (FF35) | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same | 1152-BBGA FCBGA (FF35) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 |
| Speed Grade | C6 (fastest) | C6 | C5 (~12% slower) | C5 | C5 | C4 (~25% slower) | C4 | C4 |
| Lead-Free / RoHS Suffix | G (lead-free, RoHS) | None (non-RoHS-G) | G | None | N (lead-free) | G | N | None |
| Transceivers | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Max Transceiver Rate | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps |
| Embedded Multipliers | 612 | 612 | 612 | 612 | 612 | 612 | 612 | 612 |
| Embedded Memory (bits) | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 |
| Approx Unit Price (USD) | $1,850 | $1,830 | $1,650 | $1,640 | $1,640 | $1,420 | $1,410 | $1,400 |
Key Differentiators
- Top-of-family density in the Arria II GX line with 244K LE (vs EP2AGX190FF35C6G)
- Largest FF35 package option with full 16 transceiver channels (vs EP2AGX260EF29C6G)
- C6 speed grade for highest Fmax (vs EP2AGX260FF35C5G)
- RoHS-compliant lead-free 'G' suffix (vs EP2AGX260FF35C6)
Design Notes
Use a minimum 8-layer PCB stack-up with dedicated power and ground planes for the 1152-ball FCBGA. Transceiver channels require 100-ohm differential routing with controlled 5-mil trace width and matched intra-pair skew under 5 mils. Reference the Arria II GX Transceiver Layout Guide (UG-01131) for via patterns, AC coupling capacitor placement, and stitching via density. Recommended: leave 0.2 mm of copper around the BGA escape to reduce crosstalk.
Estimated: at 85C ambient and full transceiver activity (16 channels at 6.375 Gbps), the FCBGA dissipates approximately 8-10 W. A heatsink with thermal interface material (1.0 C/W or better) is required for reliable C6-grade operation. The 35x35 mm FCBGA package theta-JA is approximately 12 C/W without airflow; with 200 LFM airflow this drops to ~8 C/W. Designers must validate with the Quartus II PowerPlay early-power estimator.
The EP2AGX260FF35C6G requires separate 0.9V core, 1.1V PLL analog, 1.5V transceiver analog, and 2.5V/3.3V IO supplies. Decoupling: place 10 nF and 0.1 uF ceramics as close as possible to every power pin, with bulk capacitors (47 uF to 220 uF) within 1 inch of the package. Power-on sequence must follow the order VCCIO before VCCINT to avoid I/O latch-up; refer to the Arria II GX handbook power-up sequencing diagram.
Each transceiver channel needs AC coupling capacitors rated for the full 6.375 Gbps data rate. Use 0402-size, NP0 dielectric, 100 nF capacitors placed within 200 mils of the transmitter pins. Pre-emphasis and equalization settings should be tuned with the Quartus II Transceiver Toolkit using a real-time eye-measurement utility. Receiver CTLE and DFE are recommended for backplanes exceeding 10 inches.
Do not confuse the EP2AGX260FF35C6G (1152-ball FF35 package) with the EP2AGX260EF29C6G (780-ball EF29 package); they share the same die but are NOT pin-compatible. JTAG chain errors at bring-up are commonly traced to TCK pull-down or TMS pull-up resistors missing near the FPGA. Verify the BSDL file against the FF35 package and confirm all unused JTAG pins are biased correctly per the JTAG Boundary-Scan Test (BST) guide.
Compliance Information
G suffix denotes lead-free / RoHS compliance per Intel datasheet. AEC-Q100 is not applicable as the part is a commercial-grade FPGA; industrial-temperature variants exist with 'I' suffix ordering codes.
