EP2AGX260FF35C6N - Arria II GX 244K LE FPGA, 1152-FBGA | Intel
MPN: EP2AGX260FF35C6N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 100 | $1580 | $158,000.00 |
| 500 | $1450 | $725,000.00 |
| 1,000 | $1320 | $1,320,000.00 |
EP2AGX260FF35C6N Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and programmable interconnect. FPGAs occupy a distinct tier in the programmable logic hierarchy (FPGA -> programmable logic -> ASIC prototyping -> digital IC -> semiconductor), enabling parallel hardware execution, deterministic latency, and post-fabrication reprogrammability. Compared with general-purpose microcontrollers, FPGAs deliver substantially higher I/O throughput and per-clock computation for data-path intensive workloads.
Key differentiating features of the EP2AGX260FF35C6N include its 244K logic-element capacity, integrated PCI Express hard IP, multi-gigabit transceivers (MGTs) supporting protocols such as PCIe Gen2, Serial RapidIO, XAUI, and CPRI, and on-chip memory blocks with hardware FIFO controllers. The 1152-FCBGA package exposes 612 user I/O pins to support wide parallel buses, external memory interfaces (DDR2/DDR3/QDRII+/RLDRAM II), and multiple high-speed serial links simultaneously.
Architecturally, the device uses a heterogeneous fabric that combines 4-input ALMs (Adaptive Logic Modules), M9K and M144K memory blocks, MLABs, and DSP blocks operating at 400 MHz fabric speed. The transceiver block delivers up to 6.375 Gbps data rate, while the hard PCIe Gen2 controller supports x1/x4 lane configurations, eliminating soft-logic timing closure on the most demanding serial interfaces.
Typical applications include high-speed serial interface bridging, digital video broadcasting, wireless baseband processing, defense and aerospace signal processing, and ASIC prototyping. The combination of high logic density, embedded transceivers, and large on-chip memory makes it well suited to throughput-bound designs that would otherwise require multiple discrete components.
When designing with this part, plan power-rail decoupling carefully - the 0.9 V core, 1.1 V PLL, and 2.5 V/3.3 V I/O supplies each require bulk and high-frequency ceramic capacitors near the balls. Use Intel Quartus II or Quartus Prime for place-and-route, and respect simultaneous-switching-output (SSO) guidelines for the 612 I/O to maintain signal-integrity margins.
This page synthesizes distributor pricing, drop-in alternatives, and practical design considerations not consolidated on any single distributor page, providing engineers with an actionable decision-support reference.
Drop-in alternatives for EP2AGX260FF35C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX260FF35C6N (same form factor and footprint) β differing in Speed Grade, Package, Operating Temperature, Transceivers, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGX260FF35C6G
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2AGX260FF35C6
β Drop-Inβ In Stock
$1795 / Unit
View Datasheet βEP2AGX260FF35C5N
β Drop-Inβ In Stock
$1545 / Unit
View Datasheet βEP2AGX260FF35C5G
β Drop-Inβ In Stock
$1395 / Unit
View Datasheet βEP2AGX260FF35C5
β Drop-Inβ In Stock
$2000 / Unit
View Datasheet βEP2AGX260FF35C4N
β Drop-Inβ In Stock
$3125 / Unit
View Datasheet βEP2AGX260FF35C6N Maximum Ratings & Electrical Characteristics
| Device Type | FPGA - Field Programmable Gate Array |
| Series | Arria II GX |
| Logic Elements | 244,188 |
| Logic Array Blocks (LABs) | 10,260 |
| User I/O Count | 612 |
| Embedded Memory Bits | 12,038,144 |
| Operating Frequency | 400 MHz |
| Process Technology | 40 nm CMOS |
| Core Supply Voltage | 0.9 V |
| Package Type | 1152-BBGA, FCBGA (FBGA-1152) |
| Package Pin Count | 1152 |
| Pin/Package Form | BALL, HBGA, SQUARE |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | Commercial (C6) |
| Speed Grade | 6 |
| RoHS Status | Compliant |
EP2AGX260FF35C6N ball, hbga, square Pin Configuration Guide
Pin configuration for EP2AGX260FF35C6N (ball, hbga, square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGX260FF35C6N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGX260FF35C6N is suitable for 6 applications: High-Speed Serial Interface Bridging, Digital Video Broadcasting Equipment, Wireless Baseband Signal Processing, Defense and Aerospace Signal Processing, ASIC Prototyping and Emulation, Industrial Imaging and Machine Vision.
High-Speed Serial Interface Bridging
The EP2AGX260FF35C6N fits high-speed serial bridge designs because its integrated multi-gigabit transceivers support up to 6.375 Gbps data rates alongside PCIe Gen2 hard IP. The 244K LE fabric absorbs protocol translation glue logic, while 12 Mbits of embedded memory buffer packet payloads during rate-matching. Placed on the line card between backplane SERDES and ASIC/ASSP, it consolidates bridging, FEC, and protocol conversion without an external PHY. Compared with multi-chip SERDES + ASSP approaches, this single-chip solution reduces BOM and PCB area.
Recommended
Digital Video Broadcasting Equipment
The EP2AGX260FF35C6N suits DVB and broadcast infrastructure requiring parallel TS (transport stream) processing at SDI rates. Its 612 user I/O pins accept multiple SDI/HD-SDI/3G-SDI inputs simultaneously, and the 244K LE fabric implements real-time MPEG/H.264 processing blocks. Embedded transceivers carry DVB-ASI or SMPTE 2022 streams to headend routers. With 12 Mbits of on-chip memory, the device buffers video frames without external SRAM, simplifying board layout and lowering system latency in studio and playout applications.
Recommended
Wireless Baseband Signal Processing
The EP2AGX260FF35C6N targets wireless baseband designs where 244K logic elements implement PHY-layer processing for LTE, WiMAX, and proprietary protocols. Its DSP blocks execute FFT/iFFT and channel coding at 400 MHz fabric speed, while 612 user I/O connect to ADC/DAC chains and CPRI/OBSAI links to the radio unit. Embedded transceivers carry CPRI up to 6.375 Gbps, eliminating an external PHY. This makes the device a strong fit for small-cell and picocell base stations requiring deterministic latency and parallel compute density.
Recommended
Defense and Aerospace Signal Processing
The EP2AGX260FF35C6N suits defense and aerospace signal-processing boards requiring high logic density and radiation-aware design. With 244K logic elements, 612 user I/O, and 12 Mbits of on-chip memory, the FPGA implements radar, EW, and SIGINT processing chains while keeping board-level component count low. The FF35 1152-FBGA package has wide defense/aerospace qualification history through the Arria II GX family. For flight-grade programs, pair with the I-grade EP2AGX260FF35I5N variant for extended temperature range.
Recommended
ASIC Prototyping and Emulation
The EP2AGX260FF35C6N serves as an ASIC prototyping vehicle because its 244K logic elements map large RTL partitions without partitioning headaches. Multi-FPGA boards can chain several Arria II GX devices through their embedded transceivers, achieving multi-million-gate emulations. 12 Mbits of embedded memory mirror ASIC SRAM blocks, while 612 user I/O expose wide test access for bring-up. Compared with ASIC tape-out iterations, this FPGA-based approach accelerates software development and verification by 3-6 months.
Recommended
Industrial Imaging and Machine Vision
The EP2AGX260FF35C6N fits high-speed industrial imaging because its 244K LE fabric implements real-time image preprocessing (filtering, thresholding, lens correction) on multi-megapixel streams. The 612 user I/O interface Camera Link, CoaXPress, or LVDS-based imagers directly, while embedded transceivers drive 10G Ethernet uplinks to inspection servers. On-chip memory blocks buffer line-scan data without external SRAM, lowering BOM cost. The commercial-grade speed grade 6 bin suits factory-floor machine-vision controllers.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX260FF35C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX260FF35C6G | EP2AGX260FF35C6 | EP2AGX260FF35C5N | EP2AGX260FF35C5G | EP2AGX260FF35C5 | EP2AGX260FF35C4N |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | FBGA-1152 (FF35) | FBGA-1152 (FF35) - same | FBGA-1152 (FF35) - same | FBGA-1152 (FF35) - same | FBGA-1152 (FF35) - same | FBGA-1152 (FF35) - same | FBGA-1152 (FF35) - same |
| Logic Elements | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 |
| Speed Grade | 6 (slowest) | 6 | 6 | 5 (faster) | 5 (faster) | 5 (faster) | 4 (fastest) |
| Temperature Grade | Commercial (C6 suffix) | Commercial | Commercial | Commercial | Commercial | Commercial | Commercial |
| Ball Finish / RoHS | Pb-free (RoHS) | Green compound (RoHS) | SnPb (non-RoHS) | Pb-free (RoHS) | Green compound (RoHS) | SnPb (non-RoHS) | Pb-free (RoHS) |
| User I/O Count | 612 | 612 | 612 | 612 | 612 | 612 | 612 |
| Embedded Memory (bits) | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 |
| Approx. Unit Price @ qty 1 | USD 1,850 | USD 1,850 (typ.) | USD 1,800 (typ., legacy) | USD 2,050 (typ., faster bin) | USD 2,050 (typ.) | USD 2,000 (typ., legacy) | USD 2,300 (typ., fastest bin) |
Key Differentiators
- Lowest unit cost in the 244K-LE Arria II GX FF35 speed-grade stack (vs EP2AGX260FF35C4N)
- Pb-free ball finish for RoHS-compliant designs (vs EP2AGX260FF35C6)
- Pin-compatible drop-in across speed grades and ball finishes (vs EP2AGX260FF35C5N)
Design Notes
Estimated: at full utilization (244K LE, 612 I/O toggling at 200 MHz, 8 transceivers at 6.375 Gbps) the Arria II GX FF35 device can consume 8-12 W from the 0.9 V core rail. Decouple the core with at least four 22 uF polymer + forty-seven 0.1 uF X7R ceramics placed within 100 mil of the balls, and separate PLL analog (1.1 V) and I/O (2.5 V/3.3 V) rails with ferrite beads. Use Intel's Early Power Estimator (EPE) before final PCB layout to size the regulator and thermal solution.
The 1152-ball FF35 FineLine BGA requires a high-density PCB stack-up with laser-drilled microvias to escape the inner rows. Per Intel layout guidelines, use at least 1.5 mil plated copper in the via barrel, 0.8 mm ball pitch-compatible fan-out, and matched-length impedance for high-speed serial lanes (100 ohm differential). Maintain a continuous reference plane under the device for power integrity and signal-integrity reasons. Consider HDI Type-3 or Type-4 stack-up for the FBGA breakout layers.
Estimated: at 10 W power dissipation in the FF35 35x35 mm package with theta-JA ~10 C/W (still air), junction temperature rises 100 C above ambient, exceeding the commercial 85 C limit. Provide forced-air cooling (200 LFM minimum) or attach a heat spreader. Industrial temperature grade (I-suffix variants) raises the operating ceiling to 100 C, but the silicon junction max must still be respected per the datasheet.
Simultaneous-switching-output (SSO) noise on the 612 user I/O can couple into the 0.9 V core rail through the package inductance. Limit the number of simultaneously switching outputs per I/O bank per the I/O bank guideline table in the Arria II GX Device Handbook. Place series-termination resistors within 200 mil of the FPGA ball for LVDS and HSTL I/O standards. Use IBIS models for board-level signal-integrity simulation before committing to PCB layout.
Do not confuse the FF35 1152-FBGA package with the EF29 package or DF25 package - all three are valid for Arria II GX but use different ball maps. Verify the exact package suffix before PCB layout. Also, speed grade numbers are inverted in marketing: lower number = faster bin, so C4N has better fmax than C6N. Always re-run static timing analysis in Quartus after migrating between speed grades, even when pinout is identical.
Compliance Information
RoHS compliant per Intel product page (Pb-free ball finish denoted by 'N' suffix). JEDEC J-STD-020 Pb-free reflow profile applies. AEC-Q100 not applicable - this is an FPGA, not an automotive analog IC.
