EP2AGX260FF35C6 - Arria II GX 244K LE FPGA, 612 I/O, FC-FBGA-1152 | Intel (Altera)
MPN: EP2AGX260FF35C6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2147.96 | $2,147.96 |
| 10 | $2098.5 | $20,985.00 |
| 100 | $1985 | $198,500.00 |
| 500 | $1870 | $935,000.00 |
| 1,000 | $1795 | $1,795,000.00 |
EP2AGX260FF35C6 Overview
A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit that can be configured by the customer or designer after manufacturing to implement arbitrary digital logic. FPGAs sit in the broader taxonomy of programmable logic devices (PLDs), themselves a sub-category of digital integrated circuits. Within Intel's product portfolio, Arria II GX occupies the mid-range tier between low-power Cyclone series and high-performance Stratix series, balancing cost, performance, and transceiver capability. The 40 nm process node enables lower static and dynamic power than the previous 65 nm generation while preserving up to 612 user I/O for high-bandwidth parallel interfaces.
Key features of the EP2AGX260FF35C6 include 244,188 logic elements organized into 10,260 Logic Array Blocks (LABs), 12,038,144 bits of embedded memory for buffers and FIFO implementations, dedicated 18x18 hardware multipliers for DSP pipelines, integrated multi-gigabit transceivers operating up to 6.375 Gbps for protocols such as PCIe Gen2, Serial RapidIO, and Gigabit Ethernet, a hard PCI Express Gen2 controller block, and rich clock management with PLLs. The -C6 speed grade and 0.9 V core supply place this part in the commercial-grade mid-speed tier of the family. With 1152 balls in a 35 mm FC-FBGA package, the device requires multilayer PCB design with controlled-impedance routing and BGA assembly capability.
From an architectural perspective, the Arria II GX series employs an island-style logic fabric with dedicated carry chains, distributed M9K memory blocks, MLAB logic-mode blocks, and variable-precision DSP blocks. Transceivers integrate hard PCS (Physical Coding Sublayer) and PMA (Physical Medium Attachment) layers, allowing soft logic to focus on user data-plane processing rather than low-level serialization. Hard memory controllers and the PCIe Gen2 controller further reduce soft-logic overhead, shortening time-to-market for designers.
Typical applications include wireless baseband and digital pre-distortion (DPD) for radio units, broadcast video processing and switching, PCIe Gen2 endpoint cards, high-speed serial backplane aggregation, and industrial imaging pipelines. The combination of mid-density logic, embedded transceivers, and PCI-SIG-certified hard IP explains why Arria II GX remains attractive for cost-sensitive serial-connectivity designs even after the family was transitioned to legacy status.
Designers should note that the FF35 FC-FBGA-1152 package requires a substantial PCB escape area and a stackup capable of routing 1.0 mm pitch BGA fanout. Multi-gigabit transceiver channels demand strict impedance control, length matching, and AC-coupling capacitor selection per Intel's Arria II GX Transceiver Layout Guidelines. Power-rail sequencing (1.0 V core, 2.5 V/3.3 V I/O banks, PLL analog supplies) must follow the datasheet Power-On Reset (POR) requirements to avoid latch-up during ramp.
This page synthesizes distributor pricing, drop-in pin-compatible speed-grade alternatives, and practical high-speed BGA layout notes that go beyond the manufacturer datasheet alone.
Drop-in alternatives for EP2AGX260FF35C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGX260FF35C6 (same form factor and footprint) — differing in Speed Grade, Operating Temperature, Mounting Type, Package, Package Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGX260FF35C6N
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2AGX260FF35C5N
✅ Drop-In✓ In Stock
$1545 / Unit
View Datasheet →EP2AGX260FF35C5
✅ Drop-In✓ In Stock
$2000 / Unit
View Datasheet →EP2AGX260FF35C4N
✅ Drop-In✓ In Stock
$3125 / Unit
View Datasheet →EP2AGX260FF35I5N
✅ Drop-In✓ In Stock
$1325 / Unit
View Datasheet →EP2AGX260FF35C6 Maximum Ratings & Electrical Characteristics
| Family | Arria II GX |
| Series | Arria II GX |
| Logic Elements | 244,188 |
| Logic Array Blocks (LABs) | 10,260 |
| Embedded Memory Bits | 12,038,144 |
| User I/O Pins | 612 |
| Number of Pins / Balls | 1152 balls |
| Package Type | 1152-BBGA, FCBGA (Flip-Chip FBGA) |
| Package Code | BGA1152, 34x34, 40 |
| Process Technology | 40 nm |
| Core Supply Voltage | 0.9 V |
| Speed Grade | C6 |
| Transceivers | Up to multi-gigabit transceivers supporting PCIe Gen2, Serial RapidIO, Gbps Ethernet |
| Operating Temperature Range | Commercial (0C to 85C) |
| Mounting Type | Surface mount (BGA, reflow) |
| RoHS Status | Compliant |
| Lifecycle Status | Not Recommended for New Designs (NRND) - legacy Intel FPGA family |
EP2AGX260FF35C6 Pin Configuration
| Pin B1 | VCC — Core supply rail (0.9 V) |
| Pin B2 | GND — Common ground reference |
| Pin AB1 | GXB_TX_p — Differential transceiver transmit positive (lane 0) |
| Pin AB2 | GXB_TX_n — Differential transceiver transmit negative (lane 0) |
| Pin AC3 | GXB_RX_p — Differential transceiver receive positive (lane 1) |
| Pin AC4 | GXB_RX_n — Differential transceiver receive negative (lane 1) |
| Pin AD5 | REFCLK_p — Differential reference clock input positive |
| Pin AD6 | REFCLK_n — Differential reference clock input negative |
| Pin AE7 | IO_BANK8A — User I/O bank 8A (3.3 V LVCMOS / SSTL / LVDS) |
| Pin AE8 | IO_BANK8B — User I/O bank 8B (3.3 V LVCMOS / SSTL / LVDS) |
| Pin AF9 | nCONFIG — Configuration control input (active low) |
| Pin AF10 | nSTATUS — Configuration status output (active low) |
| Pin AG11 | DCLK — Configuration clock input |
| Pin AG12 | DATA0 — Configuration data input |
| Pin AH13 | VCCA_PLL — PLL analog supply (2.5 V) |
| Pin AH14 | VCCD_PLL — PLL digital supply (0.9 V) |
Typical Applications
EP2AGX260FF35C6 is suitable for 6 applications: Wireless Baseband and Digital Pre-Distortion (DPD), Broadcast Video Processing and Routing, PCIe Gen2 Endpoint Cards, High-Speed Serial Backplane Aggregation, Industrial Imaging and Machine Vision Pipelines, Test and Measurement Instrumentation.
Wireless Baseband and Digital Pre-Distortion (DPD)
The EP2AGX260FF35C6 fits wireless baseband and DPD applications because of its 244,188 logic elements, 10,260 LABs, and integrated multi-gigabit transceivers supporting CPRI/OBSAI at up to 6.375 Gbps. With 612 user I/O plus hardware DSP blocks, the device can simultaneously implement forward-error-correction, crest-factor reduction, and adaptive DPD algorithms targeting remote-radio-head linearity of -55 dBc ACLR. The FC-FBGA-1152 package supplies the routing density required for wide datapath buses, while the PCIe Gen2 hard IP block enables clean connectivity to a baseband SoC. Designers typically pair this FPGA with a high-speed ADC and a power amplifier front-end module.
Recommended
Broadcast Video Processing and Routing
In broadcast video routers and switchers, the EP2AGX260FF35C6's 12,038,144 bits of embedded memory provide line-buffer and frame-store capacity for SD/HD/3G-SDI and HDMI streams. The 244K LE fabric handles real-time de-interlacing, scaling, color-space conversion, and overlay blending at 60 fps. Its multi-gigabit transceivers support 3G-SDI (2.97 Gbps) and emerging 6G/12G-SDI links, while the 612 user I/O enable parallel LVDS or DDR3 interfacing for memory-backed video processing. Compared with a CPU/GPU solution, this FPGA delivers deterministic latency essential for live-broadcast workflows. Power consumption at full logic utilization typically ranges 8-12 W with proper thermal design.
Recommended
PCIe Gen2 Endpoint Cards
The EP2AGX260FF35C6 includes a hard PCI Express Gen2 IP block that implements x4/x8 endpoints compliant with the PCI-SIG Gen2 specification at 5 Gbps per lane, removing soft-logic PCIe overhead from the user design. With 244,188 logic elements and 10,260 LABs, it can implement protocol accelerators such as NVMe controllers, FPGA-accelerated co-processors, or protocol-bridge cards. The 612 user I/O and 12 Mb embedded memory provide ample scratchpad RAM and external DDR3 interface bandwidth. The FC-FBGA-1152 package is compatible with standard x8 PCIe card form factors using appropriate heat-sink retention.
Recommended
High-Speed Serial Backplane Aggregation
Multi-gigabit transceiver aggregation is a sweet spot for the EP2AGX260FF35C6, which integrates up to 16 transceiver channels operating at 6.375 Gbps. This makes it suitable for serial backplane aggregation in telecom and datacom systems, where multiple 1G/10G links converge onto a higher-rate uplink or processing pipeline. The hard PCS/PMA blocks handle 8b/10b or 64b/66b encoding, freeing soft logic for queue management and protocol encapsulation. With 612 user I/O, the device can drive multi-lane SFP+/QSFP cages and external memory interfaces simultaneously. Engineers commonly pair this FPGA with SFP+ modules and QSFP breakout cables for system-level prototyping.
Recommended
Industrial Imaging and Machine Vision Pipelines
The EP2AGX260FF35C6 fits industrial imaging pipelines because of its 244K LE fabric, abundant memory bandwidth, and rich I/O for Camera Link, CoaXPress, and GigE Vision interfaces. With 12 Mb embedded memory plus soft DDR3 controllers, the device can buffer multi-megapixel sensor streams at 60-100 fps and perform real-time Bayer demosaicing, color correction, and feature extraction. The 612 user I/O accommodate multi-tap Camera Link and high-speed LVDS sensor interfaces, while multi-gigabit transceivers handle CoaXPress links up to 6.25 Gbps. Deterministic, low-latency processing makes it superior to CPU/GPU pipelines for in-line quality-control inspection systems.
Recommended
Test and Measurement Instrumentation
The EP2AGX260FF35C6 is widely used in bench-top test instruments such as protocol analyzers, bit-error-rate testers, and arbitrary waveform generators. Its multi-gigabit transceivers capture and replay high-speed serial traffic up to 6.375 Gbps, while the 244K LE fabric implements deep-pattern matchers, protocol-aware state machines, and on-the-fly statistics aggregation. The 12 Mb embedded memory and 612 user I/O enable large trace buffers and parallel interface probing. Compared to ASICs, the FPGA's reconfigurability lets test-equipment vendors support evolving standards such as USB 3.0, SATA, and PCIe Gen2 with a single hardware platform.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGX260FF35C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGX260FF35C6N | EP2AGX260FF35C5N | EP2AGX260FF35C5 | EP2AGX260FF35C4N | EP2AGX260FF35I5N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | FC-FBGA-1152 | FC-FBGA-1152 (same) | FC-FBGA-1152 (same) | FC-FBGA-1152 (same) | FC-FBGA-1152 (same) | FC-FBGA-1152 (same) |
| Speed Grade | C6 | C6 | C5 (-10% Fmax) | C5 (-10% Fmax) | C4 (-20% Fmax) | I5 (industrial temp) |
| Temperature Range | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Industrial (-40C to 100C) |
| Logic Elements | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 | 244,188 |
| Embedded Memory Bits | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 | 12,038,144 |
| User I/O | 612 | 612 | 612 | 612 | 612 | 612 |
| RoHS Compliant | Order N variant for RoHS | Yes (Pb-free) | Yes (Pb-free) | Order N variant for RoHS | Yes (Pb-free) | Yes (Pb-free) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Hard PCI Express Gen2 controller integrated (vs Lattice ECP3-series FPGAs without PCIe Gen2 IP)
- 6.375 Gbps multi-gigabit transceivers (vs Cyclone IV GX at 3.125 Gbps)
- 12 Mb embedded memory in mid-range tier (vs Arria V GX with similar density)
- Drop-in compatibility with N-suffixed RoHS variant (vs Other families requiring layout rework)
Design Notes
The FC-FBGA-1152 package at 1.0 mm pitch requires a high-density-interconnect (HDI) PCB stackup with at least 6-8 layers for clean BGA escape routing. Use microvia (laser-drilled) stackup with 1-2-1 or 1-2-1-2 build-up to fan out signals from the inner BGA grid to standard trace widths. Apply 50 ohm single-ended and 100 ohm differential impedance control for transceiver channels. The reference clock and high-speed transceiver routes must be length-matched to within the budget specified in the Arria II GX Transceiver Layout Guidelines (typically within 5 mils across a byte lane). Decoupling capacitors should be placed on the BGA-side of the package, with 0402-sized 0.1uF and 4.7uF MLCCs as close to the balls as the escape geometry allows.
Estimated: at full 244K LE utilization with transceiver channels active, the EP2AGX260FF35C6 can consume 10-15 W of total power per the Altera PowerPlay early-power estimator. Use a multi-rail DC-DC topology with separate supplies for 0.9 V core, 2.5 V PLL analog, 2.5 V/3.3 V I/O banks, and 1.0 V/1.2 V transceiver analog rails. Power-On-Reset (POR) sequencing must follow the datasheet: core voltage must reach stable levels before I/O and PLL supplies ramp, otherwise the device may enter an indeterminate state. Add a power-good supervisor to hold nCONFIG low until all rails are within tolerance.
The FC-FBGA-1152 package has a junction-to-ambient thermal resistance theta_JA of approximately 8-12 C/W with 4-layer JEDEC test board (per Altera package thermal datasheet, exact value [DATA_NEEDED]). At 10 W typical dissipation, the junction temperature rises roughly 100 C above ambient with no heat sink, requiring either airflow or a top-side heat sink with thermal interface material. For system-level thermal validation, run the Intel PowerPlay Power Analyzer tool against your post-place-and-route netlist and re-measure theta_JC with a thermocouple on a representative board. Exceeding 125 C junction will trigger thermal shutdown logic in the device.
Multi-gigabit transceiver channels running at 5.0-6.375 Gbps require 100-ohm differential routing with tightly controlled impedance, skew, and return-loss budgets. Place AC-coupling capacitors (typically 100 nF X7R) close to the transmitter pins, with the capacitor pad geometry tuned to maintain 100-ohm impedance through the discontinuity. Receiver channels may need a separate equalization / pre-emphasis setting via the Quartus II Transceiver Toolkit. Cross-talk mitigation requires at least 3W spacing between adjacent differential pairs and ground-guard vias along the channel. Reference the Arria II GX Transceiver Layout Guidelines for SI simulation methodology.
Avoid these common pitfalls: (1) Do not assume C5 and C6 speed-grade pin compatibility - they are pin-compatible but timing closure must be re-validated at the slower bin. (2) Do not enable transceiver channels without first configuring the reference clock PLL - the device may power up in an undefined state. (3) Do not route high-speed LVDS pairs across BGA break-out vias without stitching ground vias within 1 mm for return-path continuity. (4) Do not exceed 1.8 V on LVDS I/O configured as 2.5 V standards - check bank VCCIO against bank voltage per I/O Assignment Analyzer output.
Compliance Information
RoHS compliance requires the N-suffixed variant (e.g., EP2AGX260FF35C6N). The non-N variant may ship in legacy leaded finish. AEC-Q100 not applicable - this is a commercial/industrial-grade FPGA, not an automotive-qualified IC.
