Intel

EP2AGZ350FF35I4N - 350K LE Arria II GZ FPGA, 1152-BGA | Intel

MPN: EP2AGZ350FF35I4N ✓ Active

In Stock Ships in 1-3 business days

0.9 V Vdss 1152-ball FC-FBGA (35 mm x 35 mm) Package I4 (industrial) Speed 21,270,528 bits (21.27 Mbit) Memory

From $1995 USD / Unit

MOQ: 1 |

Price updated: 2026-09-08

Volume Pricing

Qty	Unit Price	Extended
1	$2850	$2,850.00
10	$2680	$26,800.00
100	$2450	$245,000.00
500	$2200	$1,100,000.00
1,000	$1995	$1,995,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP2AGZ350FF35I4N Overview

The Intel EP2AGZ350FF35I4N is a high-density Arria II GZ Field-Programmable Gate Array (FPGA) delivering 348,500 logic elements, 21,270,528 bits of embedded memory, and 554 user I/O pins in a 1152-ball FC-FBGA package. Built on a 40nm CMOS process, the device targets mid- to high-performance digital signal processing, high-speed serial interfacing, and memory-intensive designs that previously required ASIC-class integration.

An FPGA (Field-Programmable Gate Array) is a reconfigurable logic device containing programmable logic blocks, interconnect, and dedicated hard IP such as transceivers, memory controllers, and DSP blocks. Within the broader semiconductor taxonomy, FPGAs sit between general-purpose microcontrollers and fixed-function ASICs, offering hardware-level parallelism with the flexibility of post-silicon reconfiguration. The Arria II GZ family specifically targets transceiver-rich applications with up to 16 embedded transceivers per device and is fabricated at a 0.9V core voltage for power efficiency at high toggle rates.

Key features include 13,940 Logic Array Blocks (LABs), embedded 18x18 multipliers for DSP, dedicated memory interface circuitry supporting DDR3, and up to 16 high-speed transceivers operating up to 6.375 Gbps. The I4 speed grade and industrial temperature rating (-40C to +100C die junction) make this part suitable for harsh-environment embedded applications. The FC-FBGA-1152 package is a 35 mm x 35 mm flip-chip BGA optimized for high signal-integrity performance on multi-layer PCBs.

Architecturally, the Arria II GZ uses a logic-rich fabric paired with 8-input adaptive logic modules (ALMs), enabling efficient implementation of wide functions, register-rich pipelines, and arithmetic-intensive datapaths. Hard IP blocks for PCIe Gen2, memory controllers, and multi-gigabit transceivers offload common I/O functions from soft logic, freeing fabric resources for application logic. The 40nm process provides a favorable balance of static power, dynamic performance, and cost per logic element.

Typical applications include high-performance DSP for radar and medical imaging, 40G/100G wireline data path processing, broadcast video infrastructure, ASIC prototyping, and high-throughput data acquisition. The combination of 21 Mbits of embedded memory and 720 embedded multipliers (18x18) supports large FFTs, channelizers, and baseband processing blocks.

When designing with the EP2AGZ350FF35I4N, ensure the PCB uses a 1.0 mm BGA pitch and matched-impedance routing for transceiver lanes. The Quartus II design software (13.1 or later) is required for synthesis, place-and-route, and timing closure. Thermal management must consider a 35 x 35 mm BGA footprint with the exposed-die flip-chip construction.

This page synthesizes distributor pricing, drop-in package-matched alternatives, and practical board-design notes not found in the manufacturer datasheet, supporting both component selection and supply-chain decisions.

Drop-in alternatives for EP2AGZ350FF35I4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP2AGZ350FF35I4N (same form factor and footprint) — differing in Package, RoHS Status, Mounting Type, Logic Elements, Speed Grade.

EP2AGZ300FF35I4N

Intel

RoHS Status: Compliant

Mounting Type: Surface Mount

Logic Elements: 298,000