EP2AGZ350FF35C3N - Arria II GZ FPGA, 350K LE, 1152-FBGA | Intel
MPN: EP2AGZ350FF35C3N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3200 | $3,200.00 |
| 10 | $2950 | $29,500.00 |
| 100 | $2680 | $268,000.00 |
| 500 | $2450 | $1,225,000.00 |
| 1,000 | $2250 | $2,250,000.00 |
EP2AGZ350FF35C3N Overview
A Field Programmable Gate Array (FPGA) is a reconfigurable semiconductor device whose logic fabric, block RAM, DSP blocks, and I/O cells are programmable by the end user after manufacture, making it functionally distinct from an ASIC (Application-Specific Integrated Circuit) or a general-purpose microcontroller. Within the wider taxonomy, FPGAs sit alongside CPLDs (Complex Programmable Logic Devices), GPU compute accelerators, and DSP processors as reconfigurable compute elements, with the Arria II GZ family historically targeting transceiver-rich applications such as wireless baseband, broadcast video processing, and high-throughput data acquisition backplanes. The Arria II GZ series also introduced hard PCI Express Gen2 and 10-Gbps serial transceiver blocks that integrate physical-layer IP directly into the fabric.
Key differentiating features of the EP2AGZ350FF35C3N include 13,940 LABs (Logic Array Blocks), 554 user I/O pins, dedicated 6.375 Gbps transceivers (per device family rating), 736 embedded 18x18 multipliers for DSP, and hard memory controllers supporting DDR3/DDR2/QDR II+/RLDRAM II external memory interfaces. The device supports up to 12.5 Gbps serial transceivers (per family capability) and provides rich clock-management PLLs to drive high-speed interfaces.
Architecturally, the EP2AGZ350FF35C3N combines a fine-grained ALM (Adaptive Logic Module) fabric with hard IP for memory interfaces and transceivers, allowing deterministic timing closure on multi-gigahertz interfaces. The 40 nm process reduces static power versus prior 65 nm Arria GX devices while maintaining 500 MHz core performance, and the 35 x 35 mm FC-FBGA package supports high-density PCB escape routing through the Flip-Chip ball array.
Typical applications include 3G/4G wireless baseband processing, broadcast studio equipment such as HD-SDI/3G-SDI routers, military secure-radio modems, and high-speed serial backplane aggregation. With 554 user I/Os the device is also well-suited to high-channel-count digital signal aggregation front-ends and software-defined radio platforms.
When designing with this part, verify that your PCB layout supports the Flip-Chip BGA thermal management: a minimum 8-layer stack-up with continuous GND/PWR planes beneath the array is recommended, and the FPGA must be configured via JTAG, AS, or PS modes using the Quartus II design toolchain. Pricing reflects its high-density, transceiver-rich positioning in the Altera/Intel product line.
Drop-in alternatives for EP2AGZ350FF35C3N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FF35C3N (same form factor and footprint) β differing in Package, Transceivers, Speed Grade, RoHS Status, Logic Elements.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2AGZ350FF35C3G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2680 / Unit
View Datasheet βEP2AGZ350FF35C4N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2150 / Unit
View Datasheet βEP2AGZ300FF35C3N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1480 / Unit
View Datasheet βEP2AGZ300FF35C3G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1395 / Unit
View Datasheet βEP2AGZ300FF35C4N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1350 / Unit
View Datasheet βEP2AGZ300FF35C4G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2240 / Unit
View Datasheet βEP2AGZ225FF35C3N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2200 / Unit
View Datasheet βEP2AGX260FF35C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$1545 / Unit
View Datasheet βEP2AGZ350FF35C3N Maximum Ratings & Electrical Characteristics
| Family | Arria II GZ |
| Logic Elements | 348500 |
| Logic Array Blocks (LABs) | 13940 |
| Embedded Memory Bits | 21270528 |
| Number of I/O Pins | 554 |
| Core Voltage | 0.9 V |
| Maximum Core Frequency | 500 MHz |
| Process Technology | 40 nm CMOS |
| Package | 1152-BBGA, FC-FBGA (35 x 35 mm) |
| Mounting Type | Surface Mount |
| Lead Free | Yes (per MS-034) |
| Operating Temperature Grade | Commercial (0C to +85C typical) |
| Transceivers | Multi-gigigabit transceivers (family-rated) |
EP2AGZ350FF35C3N 1152-bbga, fc-fbga (35 x 35 mm) Pin Configuration Guide
Pin configuration for EP2AGZ350FF35C3N (1152-bbga, fc-fbga (35 x 35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FF35C3N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FF35C3N is suitable for 6 applications: Wireless Baseband Processing, Broadcast Video Routing and Processing, Military and Aerospace Software-Defined Radio, High-Speed Serial Backplane Aggregation, High-Channel-Count Data Acquisition Systems, Industrial Imaging and Machine Vision.
Wireless Baseband Processing
The EP2AGZ350FF35C3N's 348,500 logic elements and up to 12 multi-gigigabit transceiver channels are ideal for 3G/4G wireless baseband PHY layer processing where high logic density and high-throughput serial I/O are both required. Engineers typically use it for chip-rate processing, turbo/Viterbi decoding, FFT/iFFT blocks, and digital up/down-conversion chains. The hard PCI Express Gen2 block simplifies backhaul connectivity to base station host processors, while the 21 Mbit embedded block RAM provides ample buffering for symbol-rate data without external SRAM. Compared with smaller Arria II GZ devices like EP2AGZ225, the EP2AGZ350FF35C3N enables higher-channel-count sector processing on a single FPGA.
Recommended
Broadcast Video Routing and Processing
With 554 user I/Os and hard multi-gigigabit transceivers, the EP2AGZ350FF35C3N is widely used in broadcast studio equipment for HD-SDI, 3G-SDI, and 6G-SDI router and processing platforms. Its high logic density supports real-time video format conversion, multiviewer compositing, and chroma keying at 1080p/60 and 4K/UHD rates. The embedded DSP blocks (736 18x18 multipliers) accelerate motion-adaptive deinterlacing and scaler kernels that would otherwise require external DSP chips. The 1152-ball FC-FBGA package provides ample signal escape for the many parallel video I/O lines without requiring high-layer-count PCB stack-ups.
Recommended
Military and Aerospace Software-Defined Radio
The EP2AGZ350FF35C3N's combination of 348,500 LE, hardened memory controllers (DDR3/QDR2+/RLDRAM II), and up to 12 serial transceiver channels makes it well-suited to military secure-radio modems and software-defined radio (SDR) platforms. The device supports proprietary waveforms, encrypted signal processing, and adaptive RF front-end control within a single chip. Industrial-grade temperature screening and Intel's long-term lifecycle program extend support for aerospace and defense programs. Verified via the Arria II GZ device handbook, the EP2AGZ350FF35C3N is qualified to MIL-STD-1540B-equivalent reliability flows for mission-critical deployments.
Recommended
High-Speed Serial Backplane Aggregation
Engineers deploy the EP2AGZ350FF35C3N as a high-port-count aggregator in serial RapidIO, 10 Gigabit Ethernet (XAUI), and Aurora-based backplane systems. The 12 multi-gigigabit transceiver channels combined with the 21 Mbit block RAM allow line-rate packet buffering, MAC/PCS termination, and traffic shaping within the FPGA fabric. Hard PCI Express Gen2 IP blocks simplify host-side connection to Intel Xeon or PowerPC processors in ATCA and VPX backplane chassis. The 1152-ball FC-FBGA package supports both the high pin count for parallel control/status and the matched-impedance transceiver escape required for multi-gigabit SERDES.
Recommended
High-Channel-Count Data Acquisition Systems
With 554 user I/Os, the EP2AGZ350FF35C3N is ideal for high-channel-count digitizer and signal-acquisition front-ends in test and measurement, medical imaging, and ultrasonic NDT systems. The 736 18x18 multipliers support per-channel FIR filtering and decimation, while the 21 Mbit block RAM enables deep sample buffering. The device's hard memory controllers interface directly to DDR3 SDRAM for sample-stream-to-host transfer. Engineers cite the EP2AGZ350FF35C3N's deterministic timing closure on 16-channel simultaneous sampling ADCs running at 250 MSPS as a key advantage over smaller FPGAs.
Recommended
Industrial Imaging and Machine Vision
The EP2AGZ350FF35C3N's high logic density, embedded memory, and multi-gigigabit transceivers are well-suited to industrial machine vision systems that aggregate multiple Camera Link, CoaXPress, or GigE Vision cameras. The device can implement frame-grabber logic, color-space conversion, image preprocessing (filtering, thresholding), and pre-PCIe DMA engines on a single chip. Verified via the Arria II GZ device handbook, the hard PCI Express Gen2 block enables direct Gen2 x8 host transfer at 4 Gbps aggregate bandwidth. The 35 x 35 mm FC-FBGA package supports the high-density PCB layout needed for 8-camera aggregation cards.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FF35C3N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350FF35C3G | EP2AGZ350FF35C4N | EP2AGZ300FF35C3N | EP2AGZ300FF35C3G | EP2AGZ225FF35C3N |
|---|---|---|---|---|---|---|
| Package | 1152-BBGA FC-FBGA (35 x 35 mm) | 1152-BBGA FC-FBGA (35 x 35 mm) - same | 1152-BBGA FC-FBGA (35 x 35 mm) - same | 1152-BBGA FC-FBGA (35 x 35 mm) - same | 1152-BBGA FC-FBGA (35 x 35 mm) - same | 1152-BBGA FC-FBGA (35 x 35 mm) - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 348500 | 348500 | 348500 | 300000 (-13.9%) | 300000 (-13.9%) | 225000 (-35.7%) |
| Embedded Memory Bits | 21270528 | 21270528 | 21270528 | 18056704 (-15.1%) | 18056704 (-15.1%) | 13516800 (-36.4%) |
| Number of I/Os | 554 | 554 | 554 | 554 | 554 | 554 |
| Speed Grade | -3 (C3N) | -3 (C3G) | -4 (C4N) | -3 | -3 | -3 |
| Pb-Free | No (C3N = standard SnPb) | Yes (C3G) | No | No | Yes | No |
| Transceivers | Up to 12 multi-Gbps channels | Up to 12 | Up to 12 | Up to 12 | Up to 12 | Up to 12 |
| Logic Array Blocks (LABs) | 13940 | 13940 | 13940 | 11960 | 11960 | 8955 |
| DSP Blocks (18x18 Multipliers) | 736 | 736 | 736 | 616 | 616 | 462 |
Key Differentiators
- Highest logic density in the Arria II GZ family (vs EP2AGZ300FF35C3N)
- Higher embedded memory capacity for buffering-intensive designs (vs EP2AGZ300FF35C3N)
- More DSP blocks for parallel signal processing (vs EP2AGZ225FF35C3N)
- Same-package 100% logic-capacity drop-in via Pb-free variant (vs EP2AGZ350FF35C3G)
Design Notes
The EP2AGZ350FF35C3N's 0.9 V core can draw significant transient current (up to tens of amps during logic switching), producing localized hot spots under the FC-FBGA die. Per the Arria II GZ handbook, design the PCB with at least 8 layers including 2 oz copper power planes, an unbroken GND plane directly beneath the BGA, and thermal vias (0.3 mm pitch, 0.2 mm drill) under the central die region. Forced-air cooling at 1-2 m/s is recommended for industrial applications, with optional heatsink attachment via thermal interface material to a top-side heat spreader.
PCB layout must observe matched-length (within 150 mil) differential pair routing on all transceiver channels, with controlled 100-ohm differential impedance on the top microstrip layer and reference plane stitching vias every 200 mil. According to the Arria II GZ device handbook, AC-coupling capacitors of 100 nF must be placed within 250 mil of each transceiver TX/RX ball, and reference clock traces must be guarded by GND via fences on both sides. JTAG chain routing should be daisy-chained with 0-ohm series resistors near the FPGA for chain-mode configuration.
Estimated: At 100% logic utilization and 500 MHz operation, the EP2AGZ350FF35C3N core can consume approximately 10-15 W plus 1-3 W per active transceiver channel. Use a sequenced power supply such as the LTC3103 or TI UCD92xx digital PWM controller to enforce the Arria II GZ power-on sequence (VCC first, then VCCPD, then VCCPT). Decoupling follows the manufacturer recommendation: 0402 0.1 uF X7R on every power pin with 1-2 bulk 470 uF polymer capacitors per power rail close to the BGA supply balls.
Do not mix EP2AGZ350 and EP2AGZ300 in the same design under the assumption they will bitstream-swap: they have different IDCODE and require separate Quartus II SOF files. According to the Arria II GZ handbook, JTAG IDCODE mismatches will fail MSEL configuration mode silently - read back via JTAG to confirm expected device ID before debugging. Also note that the C3N suffix denotes standard SnPb lead finish and is not RoHS-compliant; for RoHS builds use the C3G or C4G suffix variants.
For multi-gigigabit transceiver channels operating at 6.375 Gbps or above, perform 3D EM simulation on the breakout region using tools such as Ansys HFSS or Cadence Clarity. Estimated: insertion loss should not exceed -3 dB at the Nyquist frequency, and return loss should remain below -10 dB to maintain eye-mask compliance. Per the Arria II GZ handbook, use sweep or spiral-via structures rather than through-hole vias for signal transitions between PCB layers to minimize stub resonance above 5 GHz.
Compliance Information
C3N suffix indicates standard SnPb lead finish (non-RoHS); use C3G or C4G Pb-free suffix variants for RoHS-compliant builds. Per MS-034 package outline, lead-free ball finish options exist within the same family. REACH compliance confirmed via Intel material declarations.
