EP2AGZ350FF35C4N - Arria II GZ FPGA, 350K LE, FC-FBGA-1152 | Intel
MPN: EP2AGZ350FF35C4N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3285.21 | $3,285.21 |
| 10 | $2950 | $29,500.00 |
| 50 | $2680 | $134,000.00 |
| 100 | $2410 | $241,000.00 |
| 250 | $2150 | $537,500.00 |
EP2AGZ350FF35C4N Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device belonging to the broader hierarchy of integrated circuits: FPGA -> programmable logic device (PLD) -> logic IC -> semiconductor. FPGAs combine configurable logic blocks (CLBs), programmable interconnect, dedicated DSP blocks, block RAM, and high-speed serial transceivers on a single die, allowing designers to implement arbitrary digital logic, parallel datapaths, and protocol engines without an ASIC tape-out. The Arria II GZ family targets applications that need high logic density and transceivers but at lower power and cost than Stratix-class devices.
Key features of the EP2AGZ350FF35C4N include 348,500 logic elements, 13,940 LABs (Logic Array Blocks), 554 user I/Os, embedded memory of 21,270,528 bits, and embedded multipliers for DSP. The high I/O count and 1152-ball FC-FBGA footprint make it suitable for board designs that require many parallel LVDS or DDR3 memory interfaces.
Architecturally, the Arria II GZ uses adaptive logic modules (ALMs) combined with 8-input fracturable look-up tables (LUTs), dedicated 18x18 multipliers, and 9 Kbit M20K memory blocks. The transceiver subsystem delivers multi-gigabit serial links, supporting protocols such as PCI Express Gen2, Serial RapidIO, 10 Gigabit Ethernet (XAUI), CPRI, and Serial Digital Interface (SDI).
Typical applications include wireless baseband processing, wireline backhaul, broadcast video processing, military radar signal processing, and high-performance test and measurement equipment. The device is also deployed in medical imaging and ASIC prototyping.
When designing with this part, pay close attention to PCB power distribution - the 0.9 V core and multiple 1.1 V/1.5 V/2.5 V/3.3 V supplies require multi-layer decoupling and a controlled-impedance stack-up. Thermal dissipation at full transceiver utilization also demands a thermal management strategy.
This page synthesizes distributor pricing, lifecycle observations, package-compatible alternatives, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP2AGZ350FF35C4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FF35C4N (same form factor and footprint) — differing in Package, Transceivers, RoHS Status, Speed Grade, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGZ350FF35C4G
✅ Drop-In✓ In Stock
$1395 / Unit
View Datasheet →EP2AGZ350FF35C3N
✅ Drop-In✓ In Stock
$2250 / Unit
View Datasheet →EP2AGZ350FF35C3G
✅ Drop-In✓ In Stock
$2680 / Unit
View Datasheet →EP2AGZ350FF35C4N Maximum Ratings & Electrical Characteristics
| Family | Arria II GZ |
| Logic Elements (LE) | 348,500 |
| Logic Array Blocks (LABs) | 13,940 |
| Embedded Memory (bits) | 21,270,528 |
| User I/Os | 554 |
| Process Technology | 40 nm |
| Core Voltage | 0.9 V |
| Maximum Fabric Frequency | 500 MHz |
| Package | 1152-ball FC-FBGA |
| Package Dimensions | 35 x 35 mm |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| Operating Temperature | Commercial (0C to +85C) |
| Speed Grade | C4 |
| Lead-Free / RoHS | Lead Free |
EP2AGZ350FF35C4N 35 x 35 mm Pin Configuration Guide
Pin configuration for EP2AGZ350FF35C4N (35 x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FF35C4N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FF35C4N is suitable for 6 applications: Wireless Baseband Processing, Wireline Backhaul and 10G Ethernet Aggregation, Broadcast Video Processing, Military Radar and Electronic Warfare, High-Performance Test and Measurement Equipment, Medical Imaging Systems.
Wireless Baseband Processing
The EP2AGZ350FF35C4N's 348,500 logic elements and 24 multi-gigabit transceivers make it well suited for wireless baseband signal processing where CPRI and OBSAI fronthaul links must be aggregated alongside fast Fourier transforms and channelization filters. At 0.9 V core on 40 nm, the device consumes less power than Stratix IV while still delivering up to 500 MHz fabric performance for high-rate baseband datapaths. The 21,270,528 bits of embedded memory are ample for storing time-domain samples, channel estimates, and intermediate buffers, while 554 user I/Os support wide parallel buses to RFICs and analog front ends. Designers typically place the FPGA between the radio card and the baseband L1 ASIC, processing IQ data and implementing physical-layer functions such as crest factor reduction and digital predistortion.
Recommended
Wireline Backhaul and 10G Ethernet Aggregation
Multi-gigabit transceivers on the EP2AGZ350FF35C4N natively support XAUI, 10GBASE-R, and Serial RapidIO, simplifying 10G Ethernet aggregation switches and routers for mobile backhaul. The 348,500 LEs provide headroom for packet classification engines, traffic managers, and MAC tables, while the 21 Mbit of embedded memory is sufficient for store-and-forward buffering at line rate. Hardware designers typically implement four to eight SFP+ ports or a single XFP interface directly to the FPGA, using the device's LVDS I/Os to interface with PHY sidebands. This application benefits from Quartus II IP cores for 10G Ethernet MAC and PCS that are validated against the Arria II GZ transceiver toolkit.
Recommended
Broadcast Video Processing
With 348,500 LEs and abundant on-chip RAM, the EP2AGZ350FF35C4N supports uncompressed HD/3G-SDI and emerging 4K video processing pipelines, including color space conversion, scaling, de-interlacing, and frame-rate conversion. The transceiver channels accept SDI streams at 270 Mb/s, 1.485 Gb/s, and 2.97 Gb/s directly without an external PHY. The 554 user I/Os connect to DDR2/DDR3 memory for buffering multiple video frames, and to HDMI or DisplayPort transmitters for output. Compared with ASIC-based broadcast designs, the FPGA provides rapid feature updates in response to evolving standards, with upgrade paths that preserve the FC-FBGA-1152 PCB.
Recommended
Military Radar and Electronic Warfare
The high logic density and DSP throughput of the EP2AGZ350FF35C4N make it a strong candidate for radar pulse compression, beamforming, and electronic countermeasure systems. Each Arria II GZ contains hundreds of 18x18 multipliers for FFT and pulse-Doppler processing, while 21 Mbits of embedded memory can be partitioned for windowed sample storage and CFAR tables. The serial transceivers are used to fan out digitized antenna channels to back-end processors. Designers in this segment value the FPGA's deterministic latency and the FPGA-to-ASIC migration path that the 40 nm process node enables. Thermal management and ruggedized packaging variants are typical considerations.
Recommended
High-Performance Test and Measurement Equipment
The 348,500 LEs and 24 transceivers in the EP2AGZ350FF35C4N are well matched to high-speed digitizers, protocol analyzers, and arbitrary waveform generators where many parallel DSP channels must be processed in real time. The 554 user I/Os are sufficient for direct connection to multiple ADC/DAC devices, while the transceivers support USB 3.0, SATA, and PCIe Gen2 backhaul to a host controller. On-chip M20K memory blocks provide low-latency waveform lookup tables, and the Quartus II DSP Builder toolkit accelerates FIR, FFT, and DDS IP development. The FC-FBGA-1152 package keeps board complexity manageable in dense test instruments.
Recommended
Medical Imaging Systems
Ultrasound, CT, and MRI systems benefit from the parallel DSP performance of the EP2AGZ350FF35C4N. Beamforming in ultrasound requires hundreds of multiply-accumulate operations per sample per channel, and the 348,500 LEs of fabric combined with dedicated hardware multipliers can process dozens of channels simultaneously. The 21 Mbits of embedded memory hold beamformed line data, envelope-detected samples, and tissue-harmonic image buffers. The transceivers connect to high-speed analog front ends and to backplane links between processing cards. Medical OEMs value the FPGA's deterministic timing for synchronization with imaging pulse sequences.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FF35C4N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350FF35C4G | EP2AGZ350FF35C3N | EP2AGZ350FF35C3G |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 1152-ball FC-FBGA (35x35 mm) | 1152-ball FC-FBGA (35x35 mm) - same | 1152-ball FC-FBGA (35x35 mm) - same | 1152-ball FC-FBGA (35x35 mm) - same |
| Logic Elements | 348,500 | 348,500 | 348,500 | 348,500 |
| Speed Grade | C4 | C4 | C3 (~10-15% slower fmax) | C3 (~10-15% slower fmax) |
| RoHS / Lead-Free Mark | Lead-free ('N' suffix) | RoHS 'G' suffix (Pb-free mark) | Lead-free 'N' suffix | RoHS 'G' suffix (Pb-free mark) |
| Embedded Memory (bits) | 21,270,528 | 21,270,528 | 21,270,528 | 21,270,528 |
| LABs | 13,940 | 13,940 | 13,940 | 13,940 |
| User I/Os | 554 | 554 | 554 | 554 |
| Process Technology | 40 nm | 40 nm | 40 nm | 40 nm |
Key Differentiators
- Maximum logic density in the Arria II GZ family (vs EP2AGZ300FF35C4N)
- Fastest C4 speed grade for maximum fmax (vs EP2AGZ350FF35C3N)
- Compatible with Quartus II v13.1 and earlier IP ecosystem (vs Arria 10 10AX115N3F40I2SG)
Design Notes
The EP2AGZ350FF35C4N requires a multi-rail power tree: 0.9 V core (high current, low noise), 1.1 V for PLL and transceiver PLLs, 2.5 V for differential I/O banks, and 3.3 V for legacy I/O and configuration. Decoupling requirements per the Arria II GZ device handbook call for hundreds of ceramic capacitors (0402/0201) placed directly under the BGA balls, plus bulk polymer or tantalum capacitors. Use the Quartus II PowerPlay early power estimator during architecture to size each rail before finalizing your DC-DC converters - the 0.9 V core in particular can draw tens of amps under maximum fabric utilization, demanding a multiphase buck controller.
At full transceiver and fabric utilization, the EP2AGZ350FF35C4N can dissipate 10-15 W. The FC-FBGA-1152 package uses an integrated heat spreader (IHS) - design the board with thermal vias under the BGA and consider a forced-air heatsink for industrial or military temperature grades. Use the Arria II GZ thermal model (junction-to-ambient theta_JA from the package datasheet) and your enclosure airflow assumption to compute the steady-state junction temperature. Estimated: typical commercial FC-FBGA-1152 theta_JA is 8-12 C/W with 200 LFM airflow; verify with Intel's thermal model.
The 1152-ball FC-FBGA at 35x35 mm requires a high-density PCB stack-up with 1.0 mm or 0.8 mm BGA pitch escape routing. Use microvia (laser-drilled) stack-ups with at least 6 layers for signal escape, 2 layers for ground, and 2 for power. Maintain 100 ohm differential impedance for LVDS and transceiver pairs, and 50 ohm single-ended for the global clock and high-speed control. Pin swapping through Quartus II helps simplify the PCB routing of large parallel buses to external memory.
Group LVDS pairs on dedicated I/O banks to meet the Arria II GZ I/O bank skew and matching requirements. Place external memory interfaces (DDR3) on the same bank group whenever possible to enable use of the dedicated DQS/DQSn delay lines. Keep high-speed transceiver channels on the dedicated transceiver banks; do not route general-purpose LVDS pairs on transceiver balls. Use the Quartus II Fitter resource utilization summary to verify I/O placement is achievable before PCB fabrication.
Do not attempt to migrate the EP2AGZ350FF35C4N design to a different package family (such as the Arria 10 FBG) without re-doing the entire PCB - the ball maps are NOT pin-compatible across families. Confirm configuration mode (AS, PS, JTAG) and select the correct EPCS or EPCQ configuration memory device with 3.3 V tolerance. Finally, verify that your Quartus II version supports the EP2AGZ350 device: Quartus II v13.1 is the last version with full Arria II GZ support.
Compliance Information
Lead-free finish confirmed per ordering code; RoHS compliance explicitly marked on 'G' suffix variant. AEC-Q100 is not applicable for FPGAs (automotive-grade variants are designated by 'A' in the ordering code).