EP2C20F256C6N - 18,752 LEs Cyclone II FPGA 256-FBGA | Intel
MPN: EP2C20F256C6N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $76.65 | $76.65 |
| 10 | $70.2 | $702.00 |
| 100 | $58.4 | $5,840.00 |
| 500 | $48.1 | $24,050.00 |
| 1,000 | $41.5 | $41,500.00 |
EP2C20F256C6N Overview
A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and embedded memory and multiplier blocks. FPGAs sit hierarchically within programmable logic devices (PLD) and are used to implement custom digital logic, signal processing pipelines, and glue logic. The Cyclone II family targets low-power, high-volume applications and uses a look-up-table (LUT) based logic architecture combined with embedded M4K RAM blocks, multiplying DSP blocks, and PLL clock management.
Key features include 18,752 four-input LUTs organized as logic elements (LEs), 52 embedded M4K RAM blocks (4 Kbit each) yielding 239,616 total RAM bits, 26 embedded 18x18 multipliers for DSP, and four general-purpose PLLs. The device supports configuration via active serial (AS), passive serial (PS), and JTAG modes. It accepts up to 16 global clock networks and provides 152 user I/O pins distributed across 8 I/O banks, each supporting LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards with hot-socketing capability.
Typical applications for the EP2C20F256C6N include industrial motor control and factory automation, video processing and display controllers, software-defined radio (SDR) front-end signal conditioning, automotive infotainment prototyping, and embedded vision pipelines. The 26 dedicated hardware multipliers enable moderate DSP workloads such as FIR filtering and image preprocessing without consuming logic resources. Designers select this device when deterministic parallel processing is needed at a unit price point lower than Cyclone III/IV or competing low-end FPGAs.
When designing with this device, observe the recommended decoupling network (100 nF + 10 Β΅F per VCCINT/VCCIO bank) and follow the Altera AN 466 application note for high-speed LVDS layout. The Cyclone II device is in production but is no longer recommended for new designs (NRND) β consult the Product Discontinuance notice for last-time-buy deadlines.
Drop-in alternatives for EP2C20F256C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C20F256C6N (same form factor and footprint) β differing in Speed Grade, Process Technology, Total RAM Bits, Package, Embedded Multipliers (18x18).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2C20F256C7N
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EP2C20F256I8N
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View Datasheet βEP4CE22F256C6N
β Drop-Inπ Reference alternative (not in catalog)
EP4CE22F256I7N
β Drop-Inπ Reference alternative (not in catalog)
10CL025YU256I7G
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View Datasheet βEP2C20F256C6N Maximum Ratings & Electrical Characteristics
| Series | Cyclone II |
| Logic Elements (LEs) | 18,752 |
| Embedded Memory Bits | 239,616 bits (52 M4K blocks) |
| Embedded Multipliers | 26 (18 x 18) |
| User I/O Pins | 152 |
| PLLs | 4 |
| Global Clock Networks | 16 |
| Package | 256-ball FineLine BGA (FBGA-256) |
| Speed Grade | C6 (commercial) |
| Process Technology | 90 nm low-k CMOS |
| Configuration Modes | AS, PS, JTAG |
| Operating Temperature | 0C to +85C (commercial) |
| Supply Voltage (VCCINT) | 1.15 V to 1.25 V (typ. 1.2 V) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Pb-free (lead-free) |
EP2C20F256C6N Pin Configuration
| Pin A1 | I/O β User I/O (bank 1) |
| Pin B2 | I/O β User I/O (bank 1) |
| Pin C3 | VCCINT β Core supply 1.2 V |
| Pin D4 | GND β Ground |
| Pin E5 | VCCIO1 β I/O bank 1 supply |
| Pin F6 | I/O β User I/O (bank 1) |
| Pin G7 | I/O β User I/O (bank 2) |
| Pin H8 | VCCIO2 β I/O bank 2 supply |
| Pin J9 | GND β Ground |
| Pin K10 | I/O β User I/O (bank 2) |
| Pin L11 | I/O β User I/O (bank 3) |
| Pin M12 | VCCIO3 β I/O bank 3 supply |
| Pin N13 | GND β Ground |
| Pin P14 | I/O β User I/O (bank 3) |
| Pin R15 | I/O β User I/O (bank 4) |
| Pin T16 | VCCIO4 β I/O bank 4 supply |
| Pin U13 | GND β Ground |
| Pin V12 | I/O β User I/O (bank 4) |
| Pin W11 | I/O β User I/O (bank 5) |
| Pin Y10 | VCCIO5 β I/O bank 5 supply |
| Pin AA9 | GND β Ground |
| Pin AB8 | I/O β User I/O (bank 5) |
| Pin AC7 | I/O β User I/O (bank 6) |
| Pin AD6 | VCCIO6 β I/O bank 6 supply |
| Pin AE5 | GND β Ground |
| Pin AF4 | I/O β User I/O (bank 6) |
| Pin AG3 | I/O β User I/O (bank 7) |
| Pin AH2 | VCCIO7 β I/O bank 7 supply |
| Pin AJ1 | GND β Ground |
| Pin AK2 | I/O β User I/O (bank 7) |
| Pin AL3 | I/O β User I/O (bank 8) |
| Pin AM4 | VCCIO8 β I/O bank 8 supply |
| Pin AN5 | GND β Ground |
| Pin AP6 | I/O β User I/O (bank 8) |
| Pin AR7 | CLK0 β Global clock input 0 |
| Pin AT8 | CLK1 β Global clock input 1 |
| Pin AU9 | CLK2 β Global clock input 2 |
| Pin AV10 | CLK3 β Global clock input 3 |
| Pin AW11 | nCONFIG β Configuration control (active low) |
| Pin AY12 | nSTATUS β Configuration status (active low) |
| Pin BA13 | CONF_DONE β Configuration done (active high) |
| Pin BB14 | TCK β JTAG test clock |
| Pin BC15 | TMS β JTAG test mode select |
| Pin BD16 | TDI β JTAG test data in |
| Pin BE17 | TDO β JTAG test data out |
| Pin BF18 | MSEL0 β Configuration mode select 0 |
| Pin BG19 | MSEL1 β Configuration mode select 1 |
| Pin BH20 | MSEL2 β Configuration mode select 2 |
| Pin BJ21 | DATA0 β Configuration data input 0 (AS/PS) |
| Pin BK22 | DCLK β Configuration clock (PS mode) |
| Pin BL23 | nCS β Serial config device chip select (AS) |
| Pin BM24 | ASDO β Serial config data output (AS) |
| Pin BN25 | VCCA_PLL1 β PLL1 analog supply |
| Pin BP26 | GNDA_PLL1 β PLL1 analog ground |
| Pin BR27 | VCCA_PLL2 β PLL2 analog supply |
| Pin BT28 | GNDA_PLL2 β PLL2 analog ground |
| Pin BU29 | VCCA_PLL3 β PLL3 analog supply |
| Pin BV30 | GNDA_PLL3 β PLL3 analog ground |
| Pin BW31 | VCCA_PLL4 β PLL4 analog supply |
| Pin BX32 | GNDA_PLL4 β PLL4 analog ground |
Typical Applications
EP2C20F256C6N is suitable for 7 applications: Industrial Motor Control and Factory Automation, Video Processing and Display Controllers, Software-Defined Radio Front-End Signal Conditioning, Automotive Infotainment Prototyping, Embedded Vision and Machine Vision Pipelines, Test and Measurement Instrumentation, Aerospace and Defense Prototyping.
Industrial Motor Control and Factory Automation
The EP2C20F256C6N fits industrial motor control applications because its 26 dedicated 18x18 hardware multipliers execute Park/Clarke transforms and space-vector PWM calculations in parallel, while the 4 PLLs derive the switching frequency from a single crystal reference. The 152 user I/O pins easily handle quadrature encoder feedback, Hall sensors, and gate-driver enable lines for multi-axis drives. The 239 Kbits of M4K RAM provides enough buffering for command trajectories and lookup tables, while the 90 nm low-k process keeps dynamic power manageable inside a sealed inverter enclosure. Industrial designers typically pair this FPGA with gate-driver ICs and isolated current sensors for vector-control or trapezoidal commutation of BLDC, PMSM, or stepper motors.
Recommended
Video Processing and Display Controllers
The EP2C20F256C6N is well matched to mid-resolution video processing pipelines because its 26 hardware multipliers implement FIR filters and color-space converters (RGB β YCbCr) without consuming general-purpose logic, while 239,616 bits of embedded RAM buffer 1-2 scanlines at VGA/WXGA resolutions. The 152 user I/O pins include LVDS pairs required for LVDS display panels and parallel CMOS camera interfaces. Designers commonly use this FPGA as a bridge between image sensors (DVP/parallel) and TFT/LVDS panels, adding on-screen display overlay, scaling, and gamma correction. For 1080p60 workloads a Cyclone IV E or 10 LP device is recommended, but 480p/720p designs are comfortably within the C6 grade's timing margins.
Recommended
Software-Defined Radio Front-End Signal Conditioning
The EP2C20F256C6N supports SDR front-end conditioning and digital up/down conversion because its 26 hardware 18x18 multipliers handle CIC and FIR filter stages at IF sample rates up to ~100 MHz, while the 4 PLLs generate multiple clock domains from a common reference. The 152 I/O pins comfortably accept parallel ADC data buses (e.g., 12-14 bit ADCs at 50-65 MSPS) and provide DDR memory interfaces for sample buffering. Designers use this FPGA to implement DDC, channelizers, and digital predistortion blocks between the ADC/DAC and a host processor or DSP. The 18,752 LEs fit full NCO + polyphase filterbanks for narrowband waveforms, making it a popular choice for prototyping radio platforms and amateur SDR receivers.
Recommended
Automotive Infotainment Prototyping
The EP2C20F256C6N is used in automotive infotainment prototyping because its programmable fabric lets engineers iterate on CAN/LIN gateway logic, audio routing, and display back-end designs without spinning an ASIC. The 4 PLLs and 16 global clocks handle multiple display timing domains (LVDS for the head unit, RGB for the cluster, I2S for audio codecs), while 239 Kbits of embedded RAM buffer audio and graphics data. Commercial-grade C6 temperature range (0 Β°C to +85 Β°C) is sufficient for cabin-mounted prototypes, but production programs should migrate to the EP2C20F256I7N industrial variant or a Cyclone IV/10 LP industrial-grade successor. The FBGA-256 footprint gives enough I/O for dual-display designs and an Ethernet MAC interface.
Recommended
Embedded Vision and Machine Vision Pipelines
The EP2C20F256C6N executes embedded vision preprocessing pipelines β Sobel edge detection, thresholding, convolution, and image rescaling β because the 26 hardware multipliers accelerate 3x3 and 5x5 spatial filters at VGA/WXGA frame rates, while 239 Kbits of M4K RAM acts as line buffers. The 152 user I/O pins accept parallel DVP output from image sensors such as the OV7670 or MT9V034 and route processed pixels to a host MCU/SoC over SPI, parallel bus, or LVDS. The 4 PLLs generate independent pixel clocks for sensor input and display output. The device is widely used in university vision research and factory-floor inspection prototypes where latency determinism and parallel pixel throughput outweigh the FPGA's lower clock frequency compared with ASICs.
Recommended
Test and Measurement Instrumentation
The EP2C20F256C6N is a fit for custom test-and-measurement instruments β protocol analyzers, logic-analyzer front ends, arbitrary waveform generators β because its 152 user I/O pins accept multiple high-speed parallel buses, and the 26 hardware multipliers implement digital filters and FFT butterfly stages at baseband. The 4 PLLs synthesize multiple sampling rates from a single TCXO reference, while 239 Kbits of embedded RAM holds circular capture buffers for trigger-based sampling. Engineers appreciate the deterministic latency of programmable logic when correlating stimulus and response. The commercial C6 temperature grade (0 Β°C to +85 Β°C) suits laboratory environments, and the FBGA-256 footprint allows dense I/O on the backplane of PXI-style instruments.
Recommended
Aerospace and Defense Prototyping
The EP2C20F256C6N supports aerospace and defense prototyping because its 18,752 LEs accommodate MIL-STD-1553, ARINC 429, and custom bus interfaces, while the 152 user I/O pins and 4 PLLs handle multiple clock domains in radar or electronic-warfare signal chains. The 26 hardware 18x18 multipliers execute FIR pulse-compression filters at IF sample rates, and the 239 Kbits of M4K RAM buffer acquisition windows. Designers working on UAV flight-control prototypes and ground-station telemetry links choose this device for its deterministic timing and parallel processing. For flight hardware the industrial-grade EP2C20F256I8N variant (-40 Β°C to +100 Β°C) is preferred, and long-lifecycle defense programs should consider migrating to the Cyclone IV GX for additional transceivers.
Recommended
Recommended Products Summary
Engineering reference data for EP2C20F256C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C20F256C7N | EP2C20F256C8N | EP2C20F256I7N | EP2C20F256I8N | EP4CE22F256C6N | EP4CE22F256I7N | 10CL025YU256I7G |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | FBGA-256 | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same footprint | FBGA-256 - same footprint | UBGA-256 - same ball count, verify pattern |
| Logic Elements | 18,752 | 18,752 | 18,752 | 18,752 | 18,752 | 22,320 | 22,320 | 25,920 |
| Embedded RAM | 239,616 bits | 239,616 bits | 239,616 bits | 239,616 bits | 239,616 bits | 594,432 bits | 594,432 bits | 594,432 bits |
| Hardware Multipliers | 26 | 26 | 26 | 26 | 26 | 66 | 66 | 66 |
| User I/O | 152 | 152 | 152 | 152 | 152 | 153 | 153 | 176 |
| Speed Grade | C6 (commercial) | C7 | C8 | I7 (industrial) | I8 (industrial) | C6 (commercial) | I7 (industrial) | I7 (industrial) |
| Operating Temperature | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C | -40C to +100C | 0C to +85C | -40C to +100C | -40C to +100C |
| Lifecycle | NRND | NRND | NRND | NRND | NRND | Active | Active | Active |
Key Differentiators
- Higher density and more multipliers than entry-level Cyclone II (vs EP2C5F256C6N)
- Drop-in compatibility with industrial-grade variants (vs EP2C20F256I7N and EP2C20F256I8N)
- Forward-migration path to Cyclone IV E for new designs (vs EP4CE22F256C6N)
- Integrated DSP multiplier blocks save logic resources (vs Discrete multiplier or DSP co-processor solutions)
Design Notes
Estimated: At VCCINT 1.2 V drawing ~500 mA core current plus VCCIO banks at 3.3 V drawing up to 100 mA total, the EP2C20F256C6N consumes roughly 0.6 W core plus 0.33 W I/O = 0.93 W typical, with peaks near 1.2 W when all 26 multipliers run at full rate. Use a 100 nF + 10 Β΅F decoupling pair per VCCINT and per VCCIO bank, placed within 5 mm of the respective balls, and a single 100 Β΅F bulk capacitor on each supply rail near the FPGA. The four PLL analog supplies (VCCA_PLL1β4) must each have their own 0.1 Β΅F + 10 Β΅F RC filter per the Cyclone II Device Handbook pin-connection guidelines.
The FBGA-256 package has a 17 x 17 ball grid at 1.0 mm pitch, so PCB design requires 0.4 mm laser-drilled micro-vias or 0.2 mm via-in-pad with solder-mask-defined (SMD) pads for reliable assembly. Route the four PLL analog supplies (VCCA_PLL1β4) as a star from a single ferrite bead, with the 0.1 Β΅F + 10 Β΅F filter cap within 3 mm of each ball. Match the length of LVDS pairs within 0.5 mm and keep the 100 Ξ© differential impedance at 100 Β±10 Ξ© to meet the Cyclone II LVDS specifications. Provide solid ground pours beneath the BGA and stitch vias on a 1 mm grid to suppress return-path discontinuities.
Do not assume that any 256-ball FineLine BGA with an 'EP2C20F' prefix is drop-in compatible β the trailing 'C6N', 'C7N', 'C8N', 'I7N', and 'I8N' suffixes encode speed grade (C6 fastest commercial, C8 slowest commercial) and temperature grade (C commercial, I industrial). Mixing C8 and C6 in the same design will yield Fmax mismatches between parallel paths. Also confirm CONFIG_MODE pin strap (MSEL[2:0]) for Active Serial (AS) vs Passive Serial (PS) configuration at PCB bring-up β incorrect MSEL values leave CONF_DONE low and the FPGA in reset.
Cyclone II LVDS receivers support up to 640 Mbps but require an external 100 Ξ© differential termination across each LVDS pair at the receiver end. Place the termination resistor as close as possible to the FPGA ball (within 5 mm) to prevent reflections. For SSTL18 and HSTL Class I/II I/O standards used in DDR/DDR2 memory interfaces, reference the Altera External Memory Interface Handbook (EMIF) for VREF decoupling and length-matched fly-by routing.
Compliance Information
Pb-free (N) per JEDEC J-STD-020 termination finish. RoHS compliance confirmed via distributor listings as of 2026-09-08. Halogen-free status not explicitly stated in distributor data and is marked unknown.
