EP2C35F672C7 - Cyclone II FPGA 33K LE 672-BGA | Intel
MPN: EP2C35F672C7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $178.12 | $178.12 |
| 10 | $165.45 | $1,654.50 |
| 100 | $148.2 | $14,820.00 |
| 500 | $132.8 | $66,400.00 |
| 1,000 | $119.95 | $119,950.00 |
EP2C35F672C7 Overview
An FPGA (Field-Programmable Gate Array) is a reconfigurable digital integrated circuit containing an array of programmable logic blocks, embedded memory blocks, phase-locked loops, and a programmable interconnect fabric. The Cyclone II family is positioned within Intel's broader programmable logic hierarchy as the entry-to-mid-range tier, sitting above the original Cyclone and below the Stratix/Arria/Cyclone IV families. FPGAs enable parallel hardware implementation of DSP, glue logic, bus bridging, and custom peripherals that would otherwise require discrete logic or an ASIC.
Key features of the EP2C35F672C7 include four phase-locked loops (PLLs) for clock synthesis and de-skew, 35 embedded 18×18 multipliers enabling up to 250 MHz DSP performance, support for external memory interfaces including DDR, DDR2, and QDRII SRAM, and Nios II embedded processor soft-core compatibility. The device is supported by the Quartus II design software and offers in-system programmability via serial or parallel configuration interfaces. The 672-BGA package exposes the device's full I/O count, enabling parallel data buses and high-speed external memory connections.
The Cyclone II architecture combines look-up-table (LUT)-based logic elements with M4K embedded memory blocks (4 Kbit each, configurable as RAM, ROM, or FIFO). The embedded multipliers are true 18×18 hardware multipliers that accelerate DSP operations such as FIR filters and FFT butterflies without consuming general logic. The PLLs support clock multiplication, division, phase shifting, and external clock feedback, which is essential for source-synchronous memory interfaces and multi-clock-domain designs.
Typical applications include industrial motor control, video surveillance and image processing, automotive infotainment pre-production, telecom line cards, low-cost software-defined radio front-end preprocessing, and education/development platforms. The combination of moderate logic density, embedded multipliers, and high I/O count makes the EP2C35 particularly attractive for designs transitioning from discrete DSP+microcontroller solutions to a single programmable device.
When designing with this device, allocate pin assignments early to match the BGA escape routing on the PCB, and use the Quartus II Pin Planner to verify I/O standards (LVTTL, LVCMOS, SSTL, LVDS) are supported on the chosen banks. The 672-BGA package requires via-in-pad or dog-bone fanout and controlled-impedance traces for high-speed signals. For new designs, evaluate the Cyclone IV E or Cyclone V families for active roadmap continuity, as Cyclone II is a legacy product family.
This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical design considerations for the EP2C35F672C7 in a single reference, complementing the official Intel Cyclone II datasheet with cross-vendor substitution data, application context, and PCB layout guidance that engineer-focused product pages typically omit.
Drop-in alternatives for EP2C35F672C7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C35F672C7 (same form factor and footprint) — differing in Speed Grade, Package, Process Technology, Operating Temperature, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C35F672C6
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP2C35F672C6N
✅ Drop-In✓ In Stock
$122.5 / Unit
View Datasheet →EP2C35F672C8N
✅ Drop-In✓ In Stock
$77.14 / Unit
View Datasheet →EP2C35F672I8N
✅ Drop-In✓ In Stock
$98.5 / Unit
View Datasheet →EP2C35F672C7 Maximum Ratings & Electrical Characteristics
| Series | Cyclone II |
| Logic Elements (LE) | 33,216 |
| Embedded Memory Bits | 483,840 bits (105 M4K blocks) |
| User I/O Count | 475 |
| Embedded 18x18 Multipliers | 35 |
| PLLs | 4 |
| Package | 672-BGA (FineLine BGA) |
| Speed Grade | 7 (commercial) |
| Process Technology | 90 nm low-k CMOS |
| Core Voltage | 1.2 V |
| Operating Temperature | 0C to +85C (commercial) |
| Configuration Interface | Serial (AS) and Parallel (PS) |
| Memory Interface Support | DDR, DDR2, QDRII SRAM |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
EP2C35F672C7 672-bga (fineline bga) Pin Configuration Guide
Pin configuration for EP2C35F672C7 (672-bga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C35F672C7.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C35F672C7 is suitable for 6 applications: Industrial Motor Control, Video Surveillance and Image Processing, Software-Defined Radio Front-End Preprocessing, Telecom Line Card Glue Logic, Medical Imaging Data Acquisition, Education and FPGA Development Platforms.
Industrial Motor Control
The EP2C35F672C7 fits industrial motor control because its 33,216 LEs and 35 embedded 18x18 multipliers provide ample DSP throughput for field-oriented control (FOC) algorithms and PWM generation at switching frequencies of 10-20 kHz. The 475 user I/Os support multiple encoder interfaces (QEP, SSI, EnDat), analog feedback channels, and gate-driver control signals. The four PLLs enable precise synchronization between PWM timers and ADC sampling clocks, critical for current-loop stability. Compared to a microcontroller plus external DSP approach, the FPGA consolidates control loops, communication stacks (EtherCAT, CAN), and safety logic in a single device, reducing BOM cost. The commercial temperature grade suits factory-floor enclosures with controlled ambient temperature.
Recommended
Video Surveillance and Image Processing
The EP2C35F672C7 supports multi-channel video surveillance with 483,840 bits of embedded RAM serving as line buffers for 720p HD video processing, and the 35 multipliers handle real-time image filtering (Sobel edge detection, motion estimation) at 30 fps. The 475 I/Os accommodate parallel camera interfaces (BT.656, BT.1120, LVDS) and DDR2 memory for frame buffering. The four PLLs generate pixel clocks and memory clocks with low jitter required for clean video capture. Compared to ASIC-based video processors, the FPGA enables algorithm updates in the field and supports multiple video standards (NTSC/PAL/HD-SDI) without hardware changes. The 672-BGA package supports the high pin count required for multi-channel deployments.
Recommended
Software-Defined Radio Front-End Preprocessing
The EP2C35F672C7 handles SDR front-end preprocessing where its 33K LEs implement digital down-conversion (DDC) chains, channelization filters, and Fast Fourier Transform (FFT) stages at baseband sample rates up to 100 MSPS. The 35 embedded 18x18 multipliers are essential for the polyphase filter banks and complex mixers used in digital channelizers. The 483 Kbits of embedded RAM store FFT twiddle factors and overlap-save buffers without external memory contention. The four PLLs generate the multiple clock domains needed for ADC sampling, DDC processing, and host interface transfer. The device's commercial speed grade 7 supports the timing closure required for 100 MSPS signal paths, and the Quartus II DSP Builder accelerates filter design.
Recommended
Telecom Line Card Glue Logic
The EP2C35F672C7 serves as glue logic on telecom line cards where it bridges legacy TDM buses (T1/E1, H.110) to modern packet-based backplanes and provides hardware acceleration for protocol termination. Its 33K LEs implement UTOPIA, POS-PHY, and Serial RapidIO interfaces without external PHY devices, and the 475 I/Os accommodate multiple T1/E1 framers and HDLC controllers. The embedded multipliers handle V.90 modem training sequences and echo-cancellation preprocessing. The 4 PLLs synthesize clocks from the backplane reference and generate the multiple TDM clock domains. The DDR2 memory controller interface allows connection to external packet buffers for traffic management.
Recommended
Medical Imaging Data Acquisition
The EP2C35F672C7 fits medical imaging front-ends such as ultrasound beamformers and endoscopy video processors where parallel DSP operations on multi-channel data streams are required. The 35 embedded 18x18 multipliers accelerate beamforming delay-and-sum operations across 64-128 channels, while the 483 Kbits of RAM buffer channel data between beamforming stages. The 475 I/Os interface to multi-channel ADC arrays (e.g. 16-channel ultrasound front-ends) and high-speed LVDS links to image-processing host processors. The four PLLs generate the precise phase-shifted clocks required for coherent beamforming. The Cyclone II is used in established FDA-cleared medical devices where design re-validation cost outweighs migration benefits.
Recommended
Education and FPGA Development Platforms
The EP2C35F672C7 is widely deployed on university and training boards (e.g. Altera DE2-115 development kit) where its 33K LEs and 475 I/Os provide sufficient resources for teaching digital design, computer architecture, and embedded systems curricula. The 672-BGA package exposes enough pins for student projects involving memory controllers, VGA/HDMI display interfaces, Ethernet MACs, and GPIO experiments. The 35 embedded multipliers enable DSP lab exercises, and the 4 PLLs demonstrate clock-management concepts. The Quartus II Web Edition (free) supports the EP2C35, making it ideal for cost-sensitive educational deployments. Established lab manuals, reference designs, and student project templates are widely available.
Recommended
Recommended Products Summary
Engineering reference data for EP2C35F672C7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C35F672C6 | EP2C35F672C6N | EP2C35F672C8N | EP2C35F672I8N |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-BGA (FineLine BGA) | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same |
| Logic Elements | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 |
| Embedded Memory (bits) | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 |
| Speed Grade | 7 (commercial) | 6 (commercial, slower) | 6 (commercial, slower, Pb-free) | 8 (commercial, slowest) | 8 (industrial, slowest) |
| Temperature Range | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Lead-Free / Pb-Free | No (standard SnPb) | No (standard SnPb) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest commercial speed grade in EP2C35 family (vs EP2C35F672C8N)
- Same silicon as C6N and C8N alternatives (vs EP2C35F672C6N)
- Commercial temperature vs industrial I-grade (vs EP2C35F672I8N)
Design Notes
The 672-BGA FineLine package requires via-in-pad or dog-bone fanout for signal escape. Use 0.4 mm pitch BGA with microvia technology (stacked or paired microvias) to route signals out of the inner ball grid. Plan PCB stackup with at least 6 layers: top BGA escape, 2 ground planes, 2 signal layers, and bottom for components. Maintain 50 ohm controlled impedance for high-speed signals (LVDS, DDR) and 100 ohm differential impedance for LVDS pairs. Use the Intel Cyclone II Board Design Guidelines for reference stackup recommendations.
The EP2C35F672C7 requires multiple supply rails: VCCINT (1.2 V core), VCCIO (3.3 V, 2.5 V, 1.8 V, or 1.5 V per bank), VCCA_PLL (2.5 V for PLLs), and VCCPD (3.3 V for pre-drivers). Decoupling requires 100 nF X7R ceramic capacitors within 100 mils of every supply pin, plus bulk 10-100 uF tantalum or polymer capacitors on each rail. Estimated: at 50% logic utilization and 100 MHz toggle rate, the core current can reach 1-1.5 A requiring a switching regulator with at least 2 A capacity on VCCINT. Use the Early Power Estimator (EPE) tool in Quartus II for accurate budget.
Common pitfalls with the EP2C35F672C7 include: (1) exceeding I/O bank VCCIO mixing limits - all I/Os in a bank must share the same VCCIO voltage, (2) forgetting to enable the clock multiplexing for PLL cascading which causes lock failures, (3) misconfiguring the configuration mode pins (MSEL) which results in the device not entering user mode, and (4) overlooking the need for a configuration device (EPCS) when using AS mode - the FPGA will not boot without proper serial flash. Always verify the configuration chain with the Quartus II programmer before debugging logic issues.
Estimated: at full logic utilization (~85%) and high toggle rate, the EP2C35F672C7 can dissipate 2-4 W requiring thermal management. The 672-BGA package has a theta_JA of approximately 15-20 C/W on a JEDEC 4-layer test board. For enclosed industrial enclosures with ambient up to 70C, attach a small heatsink or use thermal vias in the BGA land pattern to conduct heat to inner copper planes. Use the Quartus II PowerPlay Power Analyzer to compute accurate dissipation from the actual design utilization.
For DDR and DDR2 external memory interfaces, follow the Cyclone II External Memory Interface Handbook guidelines: use matched-length traces within +/- 25 mils for the byte lane, place series termination resistors (Rs) at the FPGA output for the address/command/clock signals (typically 25-33 ohm), and provide proper VREF decoupling. The DQS phase-shift circuitry requires the PLL to be configured correctly with proper feed-back and external feedback paths. Use the Quartus II TimeQuest timing analyzer with the memory interface IP to validate timing closure before PCB fabrication.
Compliance Information
The base EP2C35F672C7 uses SnPb (lead-containing) terminations and is NOT RoHS compliant. For RoHS compliance, select the EP2C35F672C6N, EP2C35F672C8N, or EP2C35F672I8N variants with the N suffix. REACH compliance is maintained across all variants. The Cyclone II family is NRD (Not Recommended for New Designs) - new designs should target Cyclone IV E or Cyclone V families.
