EP2C35F672C8 - Cyclone II FPGA, 33K LEs, 672-BGA | Altera
MPN: EP2C35F672C8 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $96.5 | $96.50 |
| 10 | $89.2 | $892.00 |
| 100 | $82.4 | $8,240.00 |
| 500 | $76.1 | $38,050.00 |
| 1,000 | $71.85 | $71,850.00 |
EP2C35F672C8 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be rewired by the end user after manufacture. FPGAs sit in the broader category of programmable logic devices (PLDs) and bridge the gap between fixed-function ASICs and software-driven microcontrollers, offering hardware-level parallelism for DSP, protocol bridging, and custom interface designs. Within Altera's (now Intel) portfolio, Cyclone II occupies the low-cost, low-power tier beneath Cyclone III/IV/V and the high-performance Stratix families.
Key features of the EP2C35F672C8 include support for up to 475 user I/O pins, four phase-locked loops (PLLs) for clock management, dedicated DDR/DDR2 memory interfaces with integrated data strobe (DQS) pins, and support for multiple I/O standards including LVDS, SSTL, and LVTTL. The 90 nm process delivers a favorable core dynamic-power profile compared with older Cyclone generations, and the 672-BGA package exposes the maximum I/O count for the EP2C35 die.
Architecturally, the device is built around LABs (Logic Array Blocks) of 16 LEs each, columns of M4K memory blocks, and DSP blocks for multiply-accumulate operations. Configuration is loaded through the active serial (AS), passive serial (PS), or JTAG interface, and the bitstream is stored in industry-standard EPCS configuration devices. The four PLLs provide frequency synthesis, phase shifting, and clock de-skew for system-level timing closure.
Typical applications include industrial motor control, video processing, software-defined radio (SDR) baseband, embedded vision, and low-cost ASIC prototyping. Designers frequently target the EP2C35F672C8 when they need 30K+ LEs with a rich DSP and memory mix at the lowest unit price in the Cyclone II lineup, and where the 672-BGA's high I/O count supports wide external memory buses and multi-standard I/O.
When designing with this device, attention must be paid to power distribution across the multiple VCCINT, VCCIO, and PLL supply rails, and to the 672-BGA PCB escape routing - the 1.0 mm pitch demands either microvia or laser-drilled via technology. Designers upgrading to Cyclone III/IV should expect pinout and supply-rail changes, so the EP2C35F672C8 is rarely a drop-in swap for newer families.
This page synthesizes distributor pricing, the device's position within the Cyclone II family, drop-in package- and speed-grade alternatives, and practical design notes not found in the standalone datasheet.
Drop-in alternatives for EP2C35F672C8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C35F672C8 (same form factor and footprint) — differing in Package, Speed Grade, Process Technology, Operating Temperature, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C35F672C8N
✅ Drop-In✓ In Stock
$77.14 / Unit
View Datasheet →EP2C35F672C7N
✅ Drop-In✓ In Stock
$98 / Unit
View Datasheet →EP2C35F672C6N
✅ Drop-In✓ In Stock
$122.5 / Unit
View Datasheet →EP2C35F672I8N
✅ Drop-In✓ In Stock
$98.5 / Unit
View Datasheet →EP2C35F672I8
✅ Drop-In✓ In Stock
$104.5 / Unit
View Datasheet →EP2C35F672C7
✅ Drop-In✓ In Stock
$119.95 / Unit
View Datasheet →EP2C35F672C6
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP2C35F672C8 Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Logic Elements (LEs) | 33,216 |
| Total RAM Bits | 483,840 |
| Embedded Multipliers (18x18) | 35 |
| User I/O Pins (max) | 475 |
| Number of PLLs | 4 |
| Package | 672-BGA (FineLine BGA, 1.0 mm pitch) |
| Speed Grade | C8 (commercial, 8 ns pin-to-pin) |
| Process Technology | 90 nm |
| Core Voltage (VCCINT) | 1.15 V - 1.25 V |
| Operating Temperature (Commercial) | 0C to +85C |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG |
| Memory Interface Support | DDR, DDR2, SDR SDRAM |
| I/O Standards | LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (lead-free package) |
EP2C35F672C8 672-bga (fineline bga, 1.0 mm pitch) Pin Configuration Guide
Pin configuration for EP2C35F672C8 (672-bga (fineline bga, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C35F672C8.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C35F672C8 is suitable for 6 applications: Industrial Motor Control, Video Processing and Display Bridging, Software-Defined Radio (SDR) Baseband, ASIC Prototyping and Emulation, Embedded Vision Systems, Legacy Industrial Communication Gateways.
Industrial Motor Control
The Altera EP2C35F672C8 is a strong fit for industrial motor-control designs where multi-axis PWM generation, encoder feedback processing, and field-oriented control (FOC) loops must run in parallel. Its 35 hardware 18x18 multipliers accelerate Park/Clarke transforms and PI controllers, while 33,216 LEs absorb custom state machines and protection logic. The 475 user I/Os in the 672-BGA expose enough pins for multi-axis gate-driver interfaces, Hall/quadrature decoders, and isolated SPI comms. The four PLLs de-skew encoder sampling clocks from the PWM timebase, improving torque-ripple performance. Compared with a microcontroller, the FPGA delivers deterministic cycle-by-cycle execution critical for safety-rated servo loops at 16 kHz to 32 kHz switching frequencies.
Recommended
Video Processing and Display Bridging
The EP2C35F672C8 is widely deployed in video-format conversion, scaling, and bridging designs where the 33K LEs absorb line buffers and color-space converters, and the 483,840 RAM bits hold multiple scan lines of pixel data. The 672-BGA's 475 user I/Os can drive wide parallel RGB/YCbCr buses, BT.656/601/1120 interfaces, and HDMI/DVI transmitters. The M4K memory blocks are ideal for line-shift buffers and chroma resampling FIFOs. The four PLLs synthesize pixel clocks at 25 MHz to 148.5 MHz from a single reference, supporting 720p and 1080p timing. Compared with an ASSP video processor, the EP2C35F672C8 lets you customize algorithms such as deinterlacing or edge enhancement at no extra cost.
Recommended
Software-Defined Radio (SDR) Baseband
The EP2C35F672C8 has long been a workhorse for low-cost software-defined radio baseband processing, especially in amateur-radio and academic prototypes. The 35 dedicated 18x18 multipliers enable real-time FFT, channelization, and digital down-conversion (DDC) pipelines, while the 483,840 bits of M4K memory hold complex sample buffers between DSP stages. The 672-BGA's high I/O count accommodates dual-channel ADC/DAC interfaces and high-speed LVDS links to RF front-ends. The 90 nm process keeps dynamic power low enough for portable SDR enclosures. Compared with a dedicated DSP, the FPGA's parallelism handles multiple simultaneous channels at baseband without throughput loss.
Recommended
ASIC Prototyping and Emulation
Designers use the EP2C35F672C8 as a low-cost ASIC prototyping platform for sub-50K-gate designs, taking advantage of 33,216 LEs and 475 user I/Os to map register-transfer level (RTL) blocks one-to-one. The 672-BGA exposes enough pins to bring out full 32-bit buses, multiple clock domains, and JTAG/trace ports. The M4K memory blocks act as direct substitutes for SRAM macros, and the 35 multipliers emulate DSP blocks. Quartus II synthesis maps standard-cell Verilog and VHDL with minimal manual intervention. Compared with a hard ASIC, the EP2C35F672C8 is reusable across projects and supports full-speed bring-up long before tape-out.
Recommended
Embedded Vision Systems
The EP2C35F672C8 is a strong fit for low-resolution embedded vision pipelines, such as industrial inspection, barcode reading, and simple machine-learning inference. The 35 hardware multipliers accelerate convolution kernels and Sobel/median filters, while 483,840 bits of M4K RAM serve as line and frame buffers between pipeline stages. The 672-BGA's 475 user I/Os support parallel image-sensor interfaces (e.g., OmniVision OV7670/OV7725), LCD outputs, and Ethernet/USB bridges. The four PLLs generate pixel clocks at any required frequency from 6 MHz to 148.5 MHz. Compared with a CPU-based vision stack, the FPGA delivers deterministic latency for closed-loop control in robotics and machine-vision cells.
Recommended
Legacy Industrial Communication Gateways
The EP2C35F672C8 is a popular platform for legacy-to-modern protocol gateways in industrial automation, bridging RS-485, CAN, Modbus RTU, PROFIBUS, and EtherCAT segments. The 33K LEs accommodate multiple soft protocol stacks in parallel, and the 35 multipliers handle CRC and error-correction tasks with low latency. The 475 user I/Os expose multiple isolated serial ports, fiber-optic transceivers, and industrial Ethernet PHYs. The 90 nm Cyclone II core operates reliably across the commercial 0C to +85C range typical of factory-floor enclosures. Compared with a discrete MCU per port, one EP2C35F672C8 consolidates a 4-to-8-port gateway into a single chip, cutting PCB area and BOM cost.
Recommended
Recommended Products Summary
Engineering reference data for EP2C35F672C8 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C35F672C8N | EP2C35F672C7N | EP2C35F672C6N | EP2C35F672I8N | EP2C35F672I8 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-BGA (FineLine BGA, 1.0 mm pitch) | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same | 672-BGA (FineLine BGA) - same |
| Logic Elements | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 |
| Speed Grade | C8 (8 ns) | C8 (8 ns) | C7 (7 ns, ~15% faster) | C6 (6 ns, ~25% faster) | C8 (8 ns) | C8 (8 ns) |
| Temperature Grade | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| Ball Finish | Leaded (SnPb) | Lead-free (RoHS) | Lead-free (RoHS) | Lead-free (RoHS) | Lead-free (RoHS) | Leaded (SnPb) |
| Embedded RAM (bits) | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 |
| Embedded 18x18 Multipliers | 35 | 35 | 35 | 35 | 35 | 35 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest-density Cyclone II with maximum I/O count (vs EP2C35F484C6N)
- C8 speed grade is the most economical tier in the family (vs EP2C35F672C6N)
- RoHS lead-free variants share the same die and footprint (vs EP2C35F672C8N)
Design Notes
The 672-FineLine BGA uses a 1.0 mm ball pitch, which exceeds the 0.5 mm escape limit of standard 4-layer 0.2 mm-pitch via-in-pad processes. Plan for 1 oz copper outer layers, microvia-in-pad or laser-drilled stacked vias, and at least a 6-layer stackup. Decoupling: place 0.1 uF and 0.01 uF X7R 0402 caps on every VCCINT/VCCIO ball within 100 mils, and a 10 uF bulk cap on each supply plane within 0.5 inch. Use a continuous GND plane under the BGA to provide a low-impedance return path for high-speed LVDS pairs.
The Cyclone II EP2C35 core (VCCINT) requires a 1.15 V to 1.25 V supply capable of delivering up to ~1.5 A under worst-case utilization; the VCCIO bank supplies (typically 1.8 V, 2.5 V, or 3.3 V depending on I/O standard) may each need 0.3 A to 0.5 A. Power sequencing: VCCINT must ramp monotonically before VCCIO, and the POR (power-on-reset) circuit holds the device in reset until all supplies are stable. Use a TL7705 or equivalent supervisor with adequate threshold hysteresis. Estimated: with 80% LE utilization at 200 MHz, expect 1.2 V x 1.2 A plus 3.3 V x 0.4 A across banks, requiring a 2-layer power tree with at least 2 oz copper on the VCCINT plane.
Three pitfalls to avoid with the EP2C35F672C8: (1) Do not confuse the 672-BGA (F672) with the 484-BGA (F484) - the BGA maps are entirely different, so PCB layouts are not interchangeable. (2) Do not assume lead-free and leaded versions are pin-compatible at the system level - although the BGA is mechanically identical, mixed-ball-finish reflow profiles can leave non-wetted joints; always use one ball finish on a given assembly. (3) Do not enable JTAG boundary-scan tests on user I/O banks that drive sensitive analog signals during configuration - the I/O pins are high-Z but internal pull-ups can inject noise into adjacent analog circuits.
Compliance Information
EP2C35F672C8 (leaded SnPb balls) is not lead-free; the EP2C35F672C8N variant is the lead-free RoHS-compliant version. Compliance certifications (RoHS, REACH, halogen-free) for the C8 variant were not present in the verified distributor pages - contact the manufacturer for the latest CoC.
