EP2C35F672C6N - 33K LE Cyclone II FPGA, 672-FBGA | Intel / Altera
MPN: EP2C35F672C6N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $193.35 | $193.35 |
| 10 | $174.02 | $1,740.20 |
| 100 | $154.68 | $15,468.00 |
| 500 | $135.35 | $67,675.00 |
| 1,000 | $122.5 | $122,500.00 |
EP2C35F672C6N Overview
What is an FPGA? A Field Programmable Gate Array (FPGA) is a programmable logic device whose architecture is built from an array of configurable logic blocks (CLBs), embedded memory blocks, multiplier/DSP blocks, and a programmable interconnect fabric. In the electronic component hierarchy, an FPGA sits between a microcontroller and a custom ASIC: like a microcontroller it is software-configurable and low-NRE, but like an ASIC it can run truly parallel logic at multi-hundred-MHz clock rates. The Cyclone II family targets cost-sensitive high-volume applications such as digital signal processing, video bridging, and custom peripheral interfaces.
Key features include 4 embedded PLL blocks for clock synthesis and skew management, 35 embedded 18×18 multipliers for DSP workloads, a 4-Mbit on-chip RAM subsystem, and support for external memory interfaces including DDR/DDR2 SDRAM and QDRII SRAM. The LVDS / LVTTL / SSTL / HSTL I/O bank architecture supports single-ended and differential signalling up to 475 I/O, with per-bank reference voltage support.
Architecturally, the Cyclone II device family uses a 4-input look-up-table (4-LUT) logic element, dedicated carry chains for fast arithmetic, and Altera's Logic Array Block (LAB) grouping of 16 LEs. Configuration is via the Altera Passive Parallel (PP), Passive Serial (PS), Active Serial (AS), or JTAG modes, with configuration bitstream loaded from EPCS serial configuration devices or a microcontroller.
Typical applications include industrial motor control, video format conversion, protocol bridging (PCI to local bus, UART to I2S), soft-core processor platforms (Nios II), and high-volume consumer electronics. The 475 I/O count and 33K LE capacity make the EP2C35F672C6N a mid-range workhorse for designs that need more logic than a CPLD but less than a high-end Cyclone IV or V device.
When designing with this part, ensure the PCB has a minimum of six PCB layers with dedicated ground and 1.2 V / 2.5 V / 3.3 V power planes to meet signal-integrity and decoupling guidelines in the Cyclone II device family handbook. The 672-FBGA requires a 1.0 mm ball pitch and reflow profile compatible with lead-free SAC alloy.
This page synthesises distributor pricing, drop-in compatible Cyclone II family members, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP2C35F672C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C35F672C6N (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Process Technology, Configuration Modes.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C35F672C8N
✅ Drop-In✓ In Stock
$77.14 / Unit
View Datasheet →EP2C50F672C8N
✅ Drop-In✓ In Stock
$148.75 / Unit
View Datasheet →EP2C35F672C7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$98 / Unit
View Datasheet →EP2C50F672C6N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$119 / Unit
View Datasheet →EP2C35F672C6N Maximum Ratings & Electrical Characteristics
| Series | Cyclone II |
| Logic Elements (LE) | 33,216 |
| Logic Cells | 33,216 |
| Total RAM Bits | 483,840 |
| Number of LABs/CLBs | 2076 |
| Number of Logic Elements / Cells | 33216 |
| Total Memory | 483840 bit |
| Number of I/O | 475 |
| Supply Voltage - Core | 1.2 V |
| Operating Temperature | 0°C to 85°C (C6 speed grade, commercial) |
| Mounting Type | Surface Mount |
| Package / Case | 672-BGA (FBGA-672, 1.0 mm pitch) |
| Process Technology | 90 nm CMOS |
| Number of PLLs | 4 |
| Number of 18x18 Multipliers | 35 |
| Logic Family | CMOS |
| RoHS Status | Lead-Free (per distributor listing) |
EP2C35F672C6N 672-bga (fbga-672, 1.0 mm pitch) Pin Configuration Guide
Pin configuration for EP2C35F672C6N (672-bga (fbga-672, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C35F672C6N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C35F672C6N is suitable for 7 applications: Industrial Motor Control, Video Format Conversion and Bridging, Protocol Bridging (PCI, UART, I2S, SPI to Ethernet), Nios II Soft-Core Embedded Processor Platforms, Test and Measurement Instrumentation, Medical Imaging Front-End Processing, Communications Infrastructure (TDM, Serial, CPRI).
Industrial Motor Control
The EP2C35F672C6N is well suited to industrial motor-control platforms where multiple PWM channels, encoder interfaces, and current-loop DSP must execute in parallel. The 35 dedicated 18×18 multipliers handle field-oriented control (FOC) math at 100 kHz PWM rates without overloading the logic fabric, while the 4 PLLs generate jitter-clean clocks for the PWM modules and Ethernet PHY. With 475 user I/O the part absorbs encoder, resolver, Hall-sensor, and gate-driver interfaces on a single chip. Industrial motor control frequently demands 15-year product lifecycle support, which the Cyclone II family explicitly provides.
Recommended
Video Format Conversion and Bridging
The EP2C35F672C6N is widely used in video format converters that bridge between HDMI, DVI, DisplayPort, LVDS, and parallel RGB sources and sinks. The 33,216 LEs and 35 multipliers support colour-space conversion (YUV ↔ RGB), scaling, deinterlacing, and frame-rate conversion in real time, while 475 I/O accommodate the wide parallel video buses typical at 1080p60. The 4 PLLs synthesise pixel clocks at 148.5 MHz (1080p) and 297 MHz (4K) without external clock generators. The 483,840 bits of embedded RAM serve as line buffers for deinterlacing, removing the need for external SDRAM in many designs.
Recommended
Protocol Bridging (PCI, UART, I2S, SPI to Ethernet)
Protocol bridges that translate between legacy industrial buses and modern Ethernet / IP networks are a canonical Cyclone II application. The 33,216 LEs absorb multiple soft UARTs, SPI masters, I2S audio bridges, and PCI targets operating concurrently, while 475 I/O provide the parallel bus width required for PCI 32-bit/33 MHz and parallel SDRAM interfaces. The 60 Kbytes of on-chip RAM implement packet buffers and FIFOs, reducing the need for external memory in low-throughput bridges. Ethernet MAC is implemented in soft logic and paired with an external PHY such as a Marvell Alaska or Micrel KSZ.
Recommended
Nios II Soft-Core Embedded Processor Platforms
The EP2C35F672C6N comfortably hosts the Altera Nios II/f (fast) soft-core processor running at 100 to 150 DMIPS with cache and tightly-coupled memory mapped into the 60-Kbyte on-chip RAM. The 4 PLLs provide the core clock plus peripheral clocks, and 475 I/O accommodate Ethernet MAC, USB, DDR/DDR2 SDRAM, and Flash interfaces. Designers use the part for industrial gateways, medical instrumentation, and any application needing a customised processor with deterministic interrupt latency not available on off-the-shelf microcontrollers.
Recommended
Test and Measurement Instrumentation
Digital oscilloscopes, logic analysers, protocol analysers, and arbitrary waveform generators frequently use the EP2C35F672C6N for high-speed ADC interface and DSP post-processing. The 35 dedicated 18×18 multipliers implement FIR filters and FFT butterfly operations in real time, and 475 I/O directly connect to 16-bit and 18-bit pipelined ADCs at 100 to 250 MSPS. The 4 PLLs generate the ADC sampling clock and the FPGA logic clock from a single reference, achieving sub-ps RMS jitter. The 60-Kbyte on-chip RAM implements deep capture buffers for transient recording.
Recommended
Medical Imaging Front-End Processing
Ultrasound beamformers, digital X-ray detector readouts, and patient-monitoring front ends use the EP2C35F672C6N for parallel DSP and high-speed I/O. The 33,216 LEs perform channel summation, envelope detection, and Hilbert transform on dozens of channels simultaneously, while 475 I/O interface to high-speed ADCs and LVDS buses. The 60-Kbyte on-chip RAM holds sample line buffers for line-by-line processing, and the 4 PLLs synchronise the beamformer clock to the transmit pulse. Long-term availability of the Cyclone II family is critical for medical device lifecycles that span 10 to 15 years.
Recommended
Communications Infrastructure (TDM, Serial, CPRI)
The EP2C35F672C6N is used in legacy communications infrastructure for T1/E1 framers, HDLC controllers, and serial-to-parallel conversion. The 35 multipliers handle CRC and scrambling at line rate, 475 I/O accommodate wide parallel TDM buses, and the 4 PLLs synthesise multiple low-jitter clocks from a single backplane reference. While modern designs prefer 28-nm Cyclone V or 10-nm Cyclone 10 devices, the Cyclone II remains in production for installed-base upgrades where the 15-year Intel supply commitment is required.
Recommended
Recommended Products Summary
Engineering reference data for EP2C35F672C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C35F672C8N | EP2C50F672C8N | EP2C35F672C7N | EP2C50F672C6N |
|---|---|---|---|---|---|
| Package | 672-BGA (FBGA-672) | 672-BGA (FBGA-672) - same | 672-BGA (FBGA-672) - same | 672-BGA (FBGA-672) - same | 672-BGA (FBGA-672) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 33,216 | 33,216 (same die) | 50,528 (+52%) | 33,216 (same die) | 50,528 (+52%) |
| Embedded RAM (bits) | 483,840 | 483,840 | 594,432 (+23%) | 483,840 | 594,432 (+23%) |
| Speed Grade | -6 (fastest) | -8 (slower) | -8 (slower) | -7 (mid) | -6 (matches) |
| Operating Temperature | 0°C to 85°C (Commercial) | 0°C to 85°C (Commercial) | 0°C to 85°C (Commercial) | 0°C to 85°C (Commercial) | 0°C to 85°C (Commercial) |
| User I/O | 475 | 475 | 450 | 475 | 450 |
| 18x18 Multipliers | 35 | 35 | 86 (+146%) | 35 | 86 (+146%) |
| PLLs | 4 | 4 | 4 | 4 | 4 |
Key Differentiators
- Highest speed grade in the 672-FBGA Cyclone II family at commercial temperature (vs EP2C35F672C8N)
- Smaller die area than EP2C50 in the same 672-FBGA package (vs EP2C50F672C8N)
- Long-term availability commitment for industrial and medical designs (vs EP2C35F484C8N)
Design Notes
Estimated: the EP2C35F672C6N core draws roughly 200 to 600 mA at 1.2 V depending on toggle rate and logic utilisation. Plan for a 1.2 V regulator rated at 1.5 A minimum with 100 mV peak-to-peak ripple; TI TPS54331 or Linear Technology LT3502 are typical choices. Add 22 uF + 0.1 uF decoupling per VCCINT pin pair, plus 4.7 uF + 0.1 uF per VCCIO bank. Mount the input and output capacitors within 5 mm of the regulator. Estimated based on typical Cyclone II power characterisation tables in CII51002.
Estimated: in a typical 60 percent utilisation design at 100 MHz core clock, the EP2C35F672C6N dissipates roughly 1.5 to 2.5 W. The 672-FBGA has a theta-JA of approximately 15 C/W on a 6-layer PCB with 36 thermal vias in the centre pad, so junction temperature rise is 22 to 38 C above ambient. In an enclosed industrial chassis at 60 C ambient, junction is at most 100 C, well within the 125 C commercial maximum. Add a centre thermal pad with 0.3 mm-pitch via array, never stich the power planes under the BGA.
Cyclone II 672-FBGA requires a minimum 6-layer PCB stack-up with dedicated 1.2 V core and ground planes on internal layers 2 and 5. The 1.0 mm ball pitch supports 0.10 mm / 0.10 mm trace and space with 0.4 mm microvia or 0.20 mm via-in-pad. Use length-matched differential pairs on all LVDS signals with 100 ohm differential impedance. According to the Cyclone II device family board design guidelines, the 36 via thermal pad array in the package centre must be soldered to a thermal land for 15 C/W theta-JA performance.
Do not forget the configuration mode pin (MSEL0/MSEL1/MSEL2) pull-up or pull-down resistors - the EP2C35F672C6N will not configure if MSELs are floating. Do not use a 2.5 V VCCIO bank driving a 3.3 V CMOS input without a level shifter; LVTTL/LVCMOS thresholds are 0.8 V / 2.0 V at 3.3 V and require VCCIO match. Always regenerate the .pof programming file with the Quartus II software matching the exact silicon revision printed on the package top marking.
Compliance Information
Lead-free FBGA-672 per distributor listings (DigiKey, Heisener, Ampheo all list Lead-Free / RoHS). AEC-Q100 not applicable for FPGAs targeting industrial/consumer; not automotive-qualified.
