EP2C35F672I8 - Cyclone II FPGA 33K LE 672-FBGA | Intel
MPN: EP2C35F672I8 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $174.28 | $174.28 |
| 10 | $156.85 | $1,568.50 |
| 100 | $134.2 | $13,420.00 |
| 500 | $118.75 | $59,375.00 |
| 1,000 | $104.5 | $104,500.00 |
EP2C35F672I8 Overview
A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer can reconfigure after manufacturing. FPGAs sit above Application-Specific Integrated Circuits (ASICs) and microcontrollers in the programmable logic taxonomy (FPGA -> programmable logic -> digital IC -> semiconductor), offering parallel hardware execution, nanosecond-level latency, and hardware-level deterministic timing that CPUs cannot match. Modern low-cost FPGAs like Cyclone II target glue-logic, protocol bridging, and DSP pre-processing where ASIC NRE is unjustified.
Key features include 35 embedded 18x18 multipliers (up to 250 MHz), four general-purpose PLLs with up to 16 output taps each, 250 MHz maximum internal clock frequency, and support for external memory interfaces including DDR, DDR2, SDR, QDRII, and SRAM. The 672-FBGA package uses 1.0 mm ball pitch with a 27x27 mm body, providing ample routing escape for high-density designs.
The Cyclone II architecture uses 4-input look-up tables (LUT4) with embedded memory bits distributed throughout the logic array. Logic elements combine LUTs, registers, carry chains, and multiplier blocks to efficiently implement arithmetic, state machines, and DSP pipelines. The fabric supports hot-socketing and PCI Express PIPE compatibility for interface bridging.
Typical applications include industrial motor control, video surveillance and image processing, automotive infotainment pre-production, telecom protocol bridging, and low-volume ASIC prototyping. The 475 user I/O accommodate parallel sensor buses and multiple high-speed serial interfaces concurrently.
When designing with this FPGA, ensure proper decoupling per Cyclone II handbook guidelines: 100 nF and 10 uF capacitors near each VCC/VCORE/GND pair, and a dedicated VCCAUX filter for PLL noise immunity. Configuration via JTAG or active serial requires correct MSEL pin strapping.
This page synthesizes distributor pricing, drop-in alternative MPNs from the same Cyclone II family, and practical design notes not collected in a single manufacturer document.
Drop-in alternatives for EP2C35F672I8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C35F672I8 (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Process Technology, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C35F672C8N
✅ Drop-In✓ In Stock
$77.14 / Unit
View Datasheet →EP2C35F672I6N
✅ Drop-In✓ In Stock
$44.8 / Unit
View Datasheet →EP2C35F672C8ES
✅ Drop-In✓ In Stock
$118 / Unit
View Datasheet →EP2C35F672C8
✅ Drop-In✓ In Stock
$71.85 / Unit
View Datasheet →EP2C35F672C7N
✅ Drop-In✓ In Stock
$98 / Unit
View Datasheet →EP2C35F672C7
✅ Drop-In✓ In Stock
$119.95 / Unit
View Datasheet →EP2C35F672C6N
✅ Drop-In✓ In Stock
$122.5 / Unit
View Datasheet →EP2C35F672C6
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP2C35F672I8 Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements | 33,216 |
| Embedded Memory (bits) | 483,840 |
| Embedded 18x18 Multipliers | 35 |
| User I/O Pins | 475 |
| PLLs | 4 |
| Process Technology | 90 nm CMOS SRAM |
| Package | 672-ball FineLine BGA (FBGA) |
| Package Code | F672 |
| Ball Pitch | 1.0 mm |
| Operating Temperature (Industrial) | -40C to +100C Tj |
| Speed Grade | 8 (C8 core) |
| Supply Voltage (Core) | 1.15 V to 1.25 V |
| Supply Voltage (I/O) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant (lead-free FBGA) |
EP2C35F672I8 f672 Pin Configuration Guide
Pin configuration for EP2C35F672I8 (f672 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C35F672I8.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C35F672I8 is suitable for 6 applications: Industrial Motor Control and Servo Drives, Video Surveillance and Image Processing, Telecom Protocol Bridging, Low-Volume ASIC Prototyping, Medical Diagnostic Imaging Front-End, Automotive Infotainment Pre-Production.
Industrial Motor Control and Servo Drives
The EP2C35F672I8 fits industrial motor control because its 35 embedded 18x18 multipliers handle Park/Clark transforms and SVPWM modulation at full servo-loop update rates (10-20 kHz), while 475 user I/O simultaneously support quadrature encoder inputs, Hall sensors, PWM outputs to gate drivers, and CAN/RS-485 fieldbus. Industrial -40C to +100C operation is mandatory for factory-floor enclosures without active cooling. Designers implement current/torque loops in dedicated fabric blocks and leave the 4 PLLs to generate precisely phased carrier frequencies for multi-axis control.
Recommended
Video Surveillance and Image Processing
For video surveillance designs, the EP2C35F672I8 offers 33,216 logic elements plus 35 DSP multipliers capable of running 2D FIR filters, motion detection, and MJPEG/MPEG-4 preprocessing at D1 (720x480) or 720p frame rates. The 672-FBGA package's 475 I/O accept parallel ITU-R BT.656 / BT.1120 camera inputs alongside Ethernet PHY connections, while embedded M4K memory blocks buffer multiple video lines simultaneously. Industrial temperature grade suits outdoor PoE camera enclosures where ambient temperatures can swing widely.
Recommended
Telecom Protocol Bridging
The EP2C35F672I8 bridges between legacy telecom interfaces (T1/E1, H.110, MVIP) and modern packet networks by implementing channelized framing, HDLC controllers, and TDM-to-Ethernet adaptation in fabric. With 475 I/O the device connects directly to multiple framer ICs (e.g., DS2155, PM4351) while the 4 PLLs generate all required TDM clocks from a single system reference. Industrial temperature and the NRND status make it ideal for long-lifecycle telecom infrastructure where 10-15 year production continuity is expected.
Recommended
Low-Volume ASIC Prototyping
The EP2C35F672I8 serves as an FPGA prototype vehicle before ASIC tape-out, giving engineers 33,216 LEs of validated silicon to validate RTL logic, clock-domain crossings, and external memory controller behavior before committing to mask costs. The 483,840 embedded RAM bits provide realistic on-chip memory modeling, while the 672-FBGA package exposes enough I/O for ASIC pad-ring emulation. Once the ASIC returns from fabrication, the same RTL is retargeted; many teams keep Cyclone II prototypes in labs for software bring-up and hardware-in-the-loop regression testing.
Recommended
Medical Diagnostic Imaging Front-End
In medical imaging front-ends (ultrasound beamformers, patient monitoring), the EP2C35F672I8 runs FIR and decimation filters on incoming ADC streams using its 35 18x18 DSP blocks, while 475 I/O accept parallel LVDS data from multi-channel ADCs. Industrial temperature operation supports portable cart-mounted diagnostic equipment. The 4 PLLs derive 40-80 MHz beamformer clocks with sub-nanosecond phase control critical for phased-array ultrasound. Reliability data and lifecycle transparency from Intel enable medical IEC 60601 qualification.
Recommended
Automotive Infotainment Pre-Production
The EP2C35F672I8 enables rapid development of automotive infotainment prototypes, where designers emulate CAN/LIN/MOST networks, drive LVDS displays, and decode compressed audio/video streams using its 33,216 logic elements and 35 multipliers. The industrial temperature grade survives harsh cabin environments. Once a design is validated, teams migrate to AEC-Q100-qualified Cyclone IV/V or ASIC platforms for production. The 475-I/O headroom accommodates multiple display outputs, touch controllers, and rear-seat entertainment buses concurrently.
Recommended
Recommended Products Summary
Engineering reference data for EP2C35F672I8 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C35F672C8N | EP2C35F672I6N | EP2C35F672C7N | EP2C35F672C6N |
|---|---|---|---|---|---|
| Package | 672-ball FBGA (F672) | 672-ball FBGA (F672) | 672-ball FBGA (F672) | 672-ball FBGA (F672) | 672-ball FBGA (F672) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Logic Elements | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 |
| Embedded Memory (bits) | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 |
| Embedded 18x18 Multipliers | 35 | 35 | 35 | 35 | 35 |
| User I/O | 475 | 475 | 475 | 475 | 475 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | C8 (8 ns) | C8 | I6 (faster) | C7 (faster) | C6 (fastest) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Industrial temperature operation for harsh environments (vs EP2C35F672C8N)
- C8 speed grade balances timing margin and cost (vs EP2C35F672C6N)
- I8 industrial speed grade vs I6 faster grade (vs EP2C35F672I6N)
- Standard part (not engineering sample) - guaranteed production (vs EP2C35F672C8ES)
Design Notes
Estimated: Power estimation for a typical Cyclone II design at 33,216 LEs utilization. Use the PowerPlay Early Power Estimator spreadsheet (not calculator) with toggling rate (~12.5% typical), temperature (85C), and clock frequency to model VCCINT and VCCAUX currents. Always provision at least 2x the calculated core current to handle inrush during configuration and worst-case user-mode operation.
The 672-FBGA package uses 1.0 mm ball pitch requiring either microvia or HDI PCB fabrication. Use a minimum 4-layer stack-up with dedicated GND and VCCINT planes, and place 100 nF plus 10 uF decoupling capacitor pairs within 2 mm of every VCCINT/GND and VCCAUX/GND pair. Dedicated PLL analog VCCA rail filtering with ferrite bead and 10 uF/100 nF LC network is mandatory to meet Cyclone II PLL jitter specifications.
MSEL[2:0] pins MUST be strapped to a valid configuration mode before power-up; floating MSEL causes undefined behavior or boot failure. Do not leave CONFIG_DONE, nSTATUS, or nCONFIG floating - they require external 10 kohm pull-ups to VCCIO (typically 3.3 V bank). Active-serial configuration via EPCS device requires correct DCLK series-termination when DCLK traces exceed 50 mm.
LVDS I/O standards require 100 ohm differential near-end termination at the receiver. The 672-FBGA breakout routing must maintain 100 ohm differential impedance with intra-pair skew below 20 ps for 1.1 Gbps LVDS operation. Use guard traces or ground shielding between adjacent LVDS pairs and single-ended signals to prevent crosstalk in the dense BGA breakout region.
Compliance Information
RoHS compliant per Altera/Intel product declarations; 'N' suffix variants explicitly denote Pb-free assembly. Not AEC-Q100 qualified - not for automotive AEC-Q100 applications. Cyclone II family predates many modern halogen-free declarations.
