EP610DM/883B - 16-Macrocell Classic EPLD, 100MHz, CDIP-24 | Intel
MPN: EP610DM/883B ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $128 | $1,280.00 |
| 100 | $112 | $11,200.00 |
| 500 | $98.5 | $49,250.00 |
| 1,000 | $87.2 | $87,200.00 |
EP610DM/883B Overview
A Classic EPLD is an early-generation programmable logic device sitting in the broader taxonomy of programmable logic: PAL -> PLA -> EPLD -> CPLD -> FPGA -> SoC FPGA. Classic EPLDs from the EP610 family use UV-erasable CMOS EPROM cells to store the logic configuration, providing non-volatile behavior without an external configuration memory. The EP610DM/883B is intended for glue-logic, address decoding, state-machine, and bus-interface replacement tasks where pin-count, deterministic timing, and military-grade reliability are required.
Key features include 16 macrocells, 24 pins total, dedicated input register paths, and a tPD propagation delay on the order of 25 ns (commercial grade). The /883B suffix indicates full MIL-STD-883 Class B screening, covering extended temperature range, burn-in, and 100% electrical test at temperature corners. The CDIP-24 ceramic package offers hermetic sealing suitable for harsh-environment deployments.
The architecture implements a sum-of-products AND/OR array feeding 16 flip-flop-backed output macrocells, with a synchronous clock network and asynchronous clear/preset support on every macrocell. This structure maps cleanly to state machines, decoder logic, and bus-arbitration functions, replacing multiple 74LS/74F TTL packages with one programmable device and reducing board area and BOM count.
Typical applications include military and avionics systems, industrial control, legacy replacement of 74-series glue logic, address decoding in VME/VXI backplanes, and radiation-tolerant logic subsystems. The /883B screening makes it suitable for programs requiring MIL-PRF-38535 qualified parts or DESC-approved sources.
When designing with this device, note that programming requires a classic EPROM-based programmer (not a JTAG interface). Logic fitting must be verified against the 16-macrocell resource limit; larger designs require migration to MAX series or modern CPLD families. Always derate switching speed at temperature extremes per MIL-STD-883 curves.
Drop-in alternatives for EP610DM/883B — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DM/883B (same form factor and footprint) — differing in Package, Operating Temperature, Family, Technology, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DC-35
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →EP610DC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-20
✅ Drop-In✓ In Stock
$15.85 / Unit
View Datasheet →EP610DC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610DC-10
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610DC35
✅ Drop-In✓ In Stock
$19.2 / Unit
View Datasheet →EP610DM/883B Maximum Ratings & Electrical Characteristics
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 |
| Total Pins | 24 |
| Dedicated Inputs | 24 |
| Architecture | AND/OR sum-of-products with flip-flop macrocells |
| Pipelined Data Rate | up to 100 MHz |
| Propagation Delay (tPD) | approximately 25 ns (commercial grade) |
| Technology | UV-erasable CMOS EPROM |
| Package | 24-pin Ceramic DIP (CDIP-24) |
| Mounting Type | Through-Hole |
| Operating Temperature | -55C to +125C (MIL-STD-883 Class B) |
| MIL Screening | MIL-STD-883 Class B (/883B) |
| Configuration Method | EPROM programmer (not JTAG) |
| Family | Altera Classic EPLD (EP610) |
EP610DM/883B Pin Configuration
| Pin 1 | I/O — Input/Output pin (macrocell or input) |
| Pin 2 | I/O — Input/Output pin |
| Pin 3 | I/O — Input/Output pin |
| Pin 4 | I/O — Input/Output pin |
| Pin 5 | I/O — Input/Output pin |
| Pin 6 | I/O — Input/Output pin |
| Pin 7 | I/O — Input/Output pin |
| Pin 8 | I/O — Input/Output pin |
| Pin 9 | I/O — Input/Output pin |
| Pin 10 | I/O — Input/Output pin |
| Pin 11 | I/O — Input/Output pin |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Input/Output pin |
| Pin 14 | I/O — Input/Output pin |
| Pin 15 | I/O — Input/Output pin |
| Pin 16 | I/O — Input/Output pin |
| Pin 17 | I/O — Input/Output pin |
| Pin 18 | I/O — Input/Output pin |
| Pin 19 | I/O — Input/Output pin |
| Pin 20 | I/O — Input/Output pin |
| Pin 21 | I/O — Input/Output pin |
| Pin 22 | I/O — Input/Output pin |
| Pin 23 | I/O — Input/Output pin |
| Pin 24 | VCC — +5V power supply |
Typical Applications
EP610DM/883B is suitable for 6 applications: Military Avionics Glue Logic, Legacy 74-Series TTL Replacement, Industrial Control State Machines, VME/VXI Backplane Address Decoding, Aerospace Radiation-Tolerant Logic, Test and Measurement Equipment.
Military Avionics Glue Logic
The EP610DM/883B's MIL-STD-883 Class B screening and CDIP-24 hermetic package make it a natural fit for military avionics where multiple 74LS-series decoder and latch packages would otherwise be required. The 16 macrocells and 24 inputs can absorb typical address-decoding, interrupt-priority, and chip-select generation functions for VME/VXI backplane interfaces. With pipelined data rates up to 100 MHz, the EP610DM/883B handles synchronous bus arbitration logic without timing violations; the deterministic tPD of approximately 25 ns allows tight setup/hold budgeting in flight-control subsystems. Designers should derate switching performance at the -55C to +125C military temperature range and verify that logic fit stays within the 16-macrocell resource limit; larger designs migrate to MAX series with PCB rework.
Recommended
Legacy 74-Series TTL Replacement
The EP610DM/883B directly replaces clusters of 74LS, 74F, and 74AS glue-logic packages in legacy systems where board respins are not feasible. Its AND/OR sum-of-products architecture maps cleanly to address decoders, multiplexers, parity generators, and bus arbiters that previously consumed 5 to 10 SSI/MSI packages per function. The 24 dedicated inputs handle multiple enable and select lines without external buffering, and the 16 flip-flop-backed macrocells preserve registered outputs needed for state retention during bus cycles. In military systems, the /883B screening ensures the replacement part survives the same environmental stress as the original TTL, removing the need for re-qualification of the surrounding subsystem. Designers should use MAX+PLUS II or AHDL to compile netlists from the original 74-series logic equations.
Recommended
Industrial Control State Machines
The EP610DM/883B's 16 macrocells, each with programmable clock, clear, and preset, support Mealy and Moore state machines for industrial PLC, motor-control, and process-control applications. Its deterministic propagation delay of approximately 25 ns simplifies timing closure in safety-critical control loops, and the hermetic CDIP-24 package tolerates the vibration, humidity, and thermal-cycling stresses found in factory-floor and outdoor installations. The 24 dedicated inputs can interface directly to 5V sensor arrays and switch-contact debouncers without external buffers, reducing BOM cost. Designers should validate that the EP610DM/883B's EPROM-based configuration matches the system's firmware-update cadence, since UV erasure and reprogramming require physical device removal.
Recommended
VME/VXI Backplane Address Decoding
The EP610DM/883B is well-suited to VME and VXI backplane address-decoding applications, where its 24 dedicated inputs accept the full 32-bit address bus plus control signals (AS, DS, AM codes) without external latches. The 16 macrocells can decode multiple address windows and generate chip-select outputs for board-level peripherals, replacing 4 to 6 discrete 74LS138/74LS139 decoder packages per slot. The pipelined 100 MHz capability supports 8 MB/s VME transactions with margin, and the /883B screening allows deployment in defense and aerospace VME chassis where commercial parts are excluded by spec. Engineers should verify timing against the VME specification's setup/hold requirements and route the device's clock input to a clean backplane-derived clock.
Recommended
Aerospace Radiation-Tolerant Logic
Although not formally RAD-hard, the EP610DM/883B's MIL-STD-883 Class B screening, hermetic ceramic package, and mature CMOS EPROM process provide a degree of resilience in low-earth-orbit and avionics subsystems where modern RAD-hard FPGAs are cost-prohibitive. The 16-macrocell resource cap is appropriate for small decoder and sequencer functions that do not need the capacity of a RAD-tolerant FPGA like the Xilinx XQR4VSX55. The CDIP-24 ceramic package's thermal mass helps stabilize junction temperature during radiation-induced single-event transients, and the deterministic combinational delay aids in error-detection window budgeting. Programs requiring formal radiation hardness should verify lot radiation data with the manufacturer rather than relying on screening alone.
Recommended
Test and Measurement Equipment
The EP610DM/883B's deterministic timing and hermetic packaging suit bench-top and field-portable test equipment operating in harsh electromagnetic and thermal environments. Its 16 macrocells can implement timing generators, pulse-width modulators, and protocol-formatting logic for legacy GPIB, RS-232, or parallel test interfaces. The /883B screening allows use in military depot test stations where MIL-spec parts are mandated, and the 24 inputs support direct connection to front-panel switch arrays and rotary encoders. Designers should note that the device's EPROM-based configuration is one-time programmable (or UV-erasable in windowed variants), so field firmware updates are not supported without device replacement.
Recommended
Recommended Products Summary
Engineering reference data for EP610DM/883B — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-35 | EP610DC-25 | EP610DC-20 | EP610DC-15 |
|---|---|---|---|---|---|
| Package | CDIP-24 (MIL-STD-883 Class B) | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Macrocells | 16 | 16 - same | 16 - same | 16 - same | 16 - same |
| Propagation Delay (tPD) | approximately 25 ns | 35 ns | 25 ns | 20 ns | 15 ns |
| MIL Screening | MIL-STD-883 Class B | Commercial (no MIL screening) | Commercial (no MIL screening) | Commercial (no MIL screening) | Commercial (no MIL screening) |
| Operating Temperature | -55C to +125C | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Configuration Method | EPROM programmer | EPROM programmer | EPROM programmer | EPROM programmer | EPROM programmer |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Typical Unit Price (qty 100) | $112 | lower (commercial, ~$40-60) | lower (commercial, ~$40-60) | lower (commercial, ~$40-60) | lower (commercial, ~$40-60) |
Key Differentiators
- MIL-STD-883 Class B screening for harsh environments (vs EP610DC-25)
- Full military temperature range (vs EP610DC-25)
- Hermetic ceramic packaging (vs EP610DC-25)
Design Notes
The EP610DM/883B is qualified for -55C to +125C operation per MIL-STD-883 Class B. The CDIP-24 ceramic package has a higher thermal resistance than plastic DIP equivalents; designers should derate switching frequency at temperature extremes and ensure adequate thermal mass in sealed enclosures. Estimated: at 100 MHz toggling with all 16 macrocells active, junction power is approximately 500 mW; verify against the manufacturer's thermal resistance figure if available in the datasheet.
Do not attempt to program the EP610DM/883B with a modern JTAG-based programmer; this family requires classic EPROM programmers such as the Altera PLDS-JT or PLDS-EP plus MAX+PLUS II or AHDL design tools. The OTP (one-time programmable) variant cannot be reprogrammed; for iterative development, use a windowed ceramic package variant that allows UV erasure. Always verify logic fit within the 16-macrocell resource cap before committing to layout.
Place decoupling capacitors (0.1 uF ceramic) as close as possible to VCC pin 24 and GND pin 12 of the CDIP-24 package. Route all 24 I/O signals with matched trace lengths if the design uses registered outputs feeding a synchronous bus. Avoid routing high-speed clocks near the ceramic package's lead frame to minimize crosstalk; the hermetic seal provides no electrical shielding advantage.
Compliance Information
MIL-STD-883 Class B screening confirmed per part suffix /883B. RoHS, REACH, lead-free, and halogen-free status not explicitly stated in the verified web data; set to 'unknown' rather than guessed. AEC-Q100 not applicable as this is a programmable logic device, not an automotive analog IC.
