EP610LI-15 - 16-Macrocell CMOS EPLD, 15ns tPD | Altera (Rochester)
MPN: EP610LI-15 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $76.05 | $76.05 |
| 10 | $68.4 | $684.00 |
| 100 | $60.85 | $6,085.00 |
| 500 | $54.2 | $27,100.00 |
| 1,000 | $48.5 | $48,500.00 |
EP610LI-15 Overview
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and pin-out predictability of PAL/GAL devices with the higher integration of early PLDs. In the system hierarchy, an EPLD sits between simple SPLDs (PAL/GAL) and CPLDs/FPGAs: it provides AND/OR array logic with user-programmable macrocells but offers a fixed architecture (no SRAM-based interconnect), making timing deterministic and easy to simulate. The EP610 family is the second-generation Classic EPLD line introduced after the EPROM-based EP1200 series, using a CMOS EPROM cell instead of a fuse, which made it re-programmable in-system via UV erasure.
Key features of the EP610LI-15 include 16 macrcells delivering up to 48 product terms per macrocell in sum-of-products form, 100% TTL-level compatibility on inputs and outputs, and a 5 V single-supply operation. Inputs are CMOS/TTL-compatible and outputs are 3-state, allowing bus-oriented designs. The device is in-system programmable via standard EPROM programmers after UV exposure through the quartz window.
Architecturally, the EP610LI-15 uses a programmable AND-OR-NOT array feeding 16 output macrocells, each containing a flip-flop and output enable. The fixed interconnect eliminates the routing-variation headaches of FPGAs and gives predictable tCO and tSU timing - useful for legacy glue-logic replacement in industrial controllers, telecom backplanes, and military refresh programs. Today the part is supported as a long-term sustainment product by Rochester Electronics, the authorized Altera/Intel legacy distributor, with 2917 units in stock per the LCSC listing as of 2026-09-10.
Typical applications include address decoding in 8086/68K microprocessor systems, peripheral glue logic in VMEbus designs, state-machine controllers for industrial automation, and TTL-to-CMOS logic replacement in legacy telecom equipment. Its deterministic timing also makes it suitable for instrumentation front-ends where predictable propagation delay matters.
When designing with this device, mind the 15 ns tPD budget: at 40 MHz bus rates the device is borderline, so allow one wait state if driving a fast microprocessor. The DIP-24 ceramic package requires a socket if UV erasure is planned, since desoldering a ceramic DIP repeatedly will damage pads.
This page synthesizes distributor stock, lifecycle status, and drop-in same-family alternatives (EP610LI-12, EP610LC-15) not found in a single source on the manufacturer datasheet.
Drop-in alternatives for EP610LI-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LI-15 (same form factor and footprint) β differing in Package, Operating Temperature, Programming Method, Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610LC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$4.65 / Unit
View Datasheet βEP610LI-12
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP610DC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.95 / Unit
View Datasheet βEP610DI-15
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP610ILC-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.2 / Unit
View Datasheet βEP610IDC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.95 / Unit
View Datasheet βEP610LI-15 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD EP610 |
| Macrocells | 16 |
| Propagation Delay (tPD) | 15 ns |
| Counter Frequency (fCNT) | 83.3 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0 C to +70 C (commercial, "I" grade) |
| Process Technology | CMOS EPROM (UV-erasable) |
| Package | 24-pin ceramic DIP, side-brazed, windowed (DIP-24) |
| Pin Count | 24 |
| Programming Method | UV erase + EPROM programmer |
| Logic Blocks | AND/OR array, 16 output macrocells |
| I/O Standard | TTL/CMOS compatible |
| Output Type | 3-state |
| RoHS Status | Non-compliant (ceramic DIP, SnPb finish typical) |
| Manufacturer (current) | Rochester Electronics (authorized Altera legacy distributor) |
EP610LI-15 Pin Configuration
| Pin 1 | I/O0 β Input/Output macrocell 0 |
| Pin 2 | I/O1 β Input/Output macrocell 1 |
| Pin 3 | I/O2 β Input/Output macrocell 2 |
| Pin 4 | I/O3 β Input/Output macrocell 3 |
| Pin 5 | I/O4 β Input/Output macrocell 4 |
| Pin 6 | I/O5 β Input/Output macrocell 5 |
| Pin 7 | I/O6 β Input/Output macrocell 6 |
| Pin 8 | I/O7 β Input/Output macrocell 7 |
| Pin 9 | I/O8 β Input/Output macrocell 8 |
| Pin 10 | I/O9 β Input/Output macrocell 9 |
| Pin 11 | I/O10 β Input/Output macrocell 10 |
| Pin 12 | GND β Ground |
| Pin 13 | I/O11 β Input/Output macrocell 11 |
| Pin 14 | I/O12 β Input/Output macrocell 12 |
| Pin 15 | I/O13 β Input/Output macrocell 13 |
| Pin 16 | I/O14 β Input/Output macrocell 14 |
| Pin 17 | I/O15 β Input/Output macrocell 15 |
| Pin 18 | OE1 β Output Enable 1 (active low) |
| Pin 19 | OE2 β Output Enable 2 (active low) |
| Pin 20 | CLK β Global clock input |
| Pin 21 | CLR β Asynchronous clear (active high) |
| Pin 22 | NC β Not connected (per datasheet) |
| Pin 23 | NC β Not connected (per datasheet) |
| Pin 24 | VCC β +5 V supply |
Typical Applications
EP610LI-15 is suitable for 7 applications: Microprocessor Address Decoding, VMEbus Peripheral Glue Logic, Industrial State-Machine Controller, TTL-to-CMOS Logic Replacement, Legacy Telecom Backplane Interface, Military/Aerospace Refresh Programs, Test & Measurement Front-End Logic.
Microprocessor Address Decoding
The EP610LI-15's 16 macrocells and 15 ns tPD make it well suited for address decoding in 8086/68K/VMEbus microprocessor systems. With 3-state outputs and individual OE control, multiple EP610s can share a bus without external glue logic. The 15 ns propagation delay fits 8 MHz bus designs with comfortable margin, while 12 MHz and faster buses can step up to the EP610LI-12 (12 ns tPD) drop-in. Compared with discrete 74LS/74F TTL decoder trees, the EP610LI-15 collapses multiple decoder ICs into one part and lets designers iterate logic via UV erasure rather than wire-wrap changes. Reference design: Intel 8086 minimum-mode system with EP610LI-15 decoding A19-A0 into eight chip selects.
Recommended
VMEbus Peripheral Glue Logic
In legacy VMEbus backplanes, the EP610LI-15 acts as a deterministic glue-logic device between VMEbus interface ICs and on-board peripherals. Its fixed AND/OR architecture gives exact, simulator-verifiable timing - critical for VMEbus DTACK* arbitration handshakes where setup-time violations cause intermittent bus errors. The 83.3 MHz fCNT supports state machines running at full VMEbus 8 MHz/16-bit cycle rates, and the 3-state outputs let the device drive VMEbus data lines directly with proper bus-arbiter coordination. The 24-pin DIP package fits legacy VME single-height cards where board space is constrained and through-hole parts are preferred for field-replaceability.
Recommended
Industrial State-Machine Controller
Factory-automation controllers built around 8051/Z80 microcontrollers often need compact, deterministic state machines for sequential I/O control. The EP610LI-15's 16 macrocells can implement 4-5 concurrent state machines in a single 24-pin package, replacing dozens of TTL MSI parts. Its commercial 0C to +70C temperature range fits climate-controlled control cabinets, and the CMOS process gives lower power dissipation than bipolar PAL alternatives - important in enclosed panels. For harsher environments, the industrial-temp EP610ILC-10 (same footprint, 10 ns tPD) or EP610DI-15 ceramic variants are drop-in upgrades within the same family.
Recommended
TTL-to-CMOS Logic Replacement
The EP610LI-15 lets engineers replace aging 74LS/74F/74AS TTL MSI/SSI logic trees with a single re-programmable CMOS part, simplifying BOM and reducing power consumption. Each macrocell can synthesize any 4- or 8-input AND-OR-INVERT function, while the 3-state outputs replace discrete 74LS244/74LS245 buffers. The 15 ns tPD is comparable to 74LS154 (18 ns) and 74LS138 (15-20 ns) decoders, making the EP610LI-15 a timing-compatible drop-in replacement for many TTL decoder/demultiplexer functions. For OTP production runs, the EP610LC-15 plastic DIP is preferred; for prototype work the EP610LI-15 windowed ceramic allows UV erasure and re-use.
Recommended
Legacy Telecom Backplane Interface
Telecom OEMs maintaining installed-base equipment (central-office switches, multiplexers) often need exact replacement parts for boards designed in the late 1980s and early 1990s around Classic EPLDs. The EP610LI-15's deterministic timing lets it reproduce original timing budgets bit-for-bit, avoiding recertification of the surrounding system. Its 24-pin ceramic DIP form factor matches the through-hole assembly used on legacy backplane daughter cards, where SMD migration would require board redesign. Rochester Electronics supplies this part today as authorized Altera legacy inventory, ensuring continued availability for telecom sustainment programs through 2030 and beyond.
Recommended
Military/Aerospace Refresh Programs
Avionics and military electronics with 30-year service lives require exact reproduction of legacy logic designs. The EP610LI-15's ceramic side-brazed DIP package meets the temperature-cycling and hermeticity requirements of MIL-STD-883 screening programs, and its UV-erasable window allows bench reprogramming during depot-level maintenance. The 15 ns tPD fits MIL-STD-1553 databus decoder interfaces (1 MHz) and ARINC 429 line-receiver state machines with ample margin. For higher-reliability screening (e.g., 883B), the EP610DM/883B variant in the same package family is the certified upgrade path - same pinout, same architecture, full MIL processing.
Recommended
Test & Measurement Front-End Logic
Bench-top instruments (logic analyzers, protocol testers, frequency counters) use the EP610LI-15 to generate precisely-timed control waveforms around ADC/DAC front-ends. The deterministic 15 ns tPD lets designers calculate exact strobe-to-data timing without statistical timing closure, which is critical when correlating captured waveforms with sampled data. Each macrocell can implement a counter stage, register, or decoder, supporting up to 16 channels of sequenced control in one device. The 83.3 MHz fCNT accommodates high-speed trigger logic up to 80 MHz, and the 3-state outputs let the device share backplane buses with other measurement modules.
Recommended
Recommended Products Summary
Engineering reference data for EP610LI-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LC-15 | EP610LI-12 | EP610DC-15 | EP610DI-15 |
|---|---|---|---|---|---|
| Brand | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) |
| Package | CDIP-24 (windowed) | PDIP-24 - same footprint | CDIP-24 (windowed) - same | PDIP-24 - same footprint | CDIP-24 (windowed) - same |
| Macrocells | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 12 ns (-20%) | 15 ns | 15 ns |
| Temperature Grade | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Industrial -40C to +85C |
| Programming Method | UV-erasable (windowed) | OTP (plastic DIP, no window) | UV-erasable (windowed) | OTP (plastic DIP) | UV-erasable (windowed) |
| Lifecycle Status | Last-time-buy (Rochester) | Last-time-buy (Rochester) | Last-time-buy (Rochester) | Last-time-buy (Rochester) | Last-time-buy (Rochester) |
| RoHS Compliance | Non-compliant (SnPb ceramic) | Compliant (plastic DIP) | Non-compliant (SnPb ceramic) | Compliant (plastic DIP) | Non-compliant (SnPb ceramic) |
Key Differentiators
- UV-erasable ceramic package enables in-house reprogramming (vs EP610LC-15)
- 15 ns tPD is timing-compatible with 74LS TTL decoders (vs EP610DC-25 (slower 25 ns grade))
- Long-term sustainment availability via Rochester Electronics (vs Generic EPROM-based EPLDs)
Design Notes
Estimated: For the EP610LI-15 in a 24-pin ceramic DIP, install a low-profile machined-pin IC socket (e.g., Aries 24-3554 or equivalent) on the PCB rather than soldering the part directly. UV erasure requires removing the part from the board, and repeated desoldering of a ceramic DIP will delaminate the PCB pads. The socket should have gold-plated contacts to maintain low contact resistance over decades of insertion cycles. Apply a quartz-window cover sticker if the device is exposed to fluorescent lighting for extended periods to prevent inadvertent UV erasure.
Estimated: A common design pitfall is using the EP610LI-15 in a 16 MHz or faster 8086/68K bus without a wait state. At 16 MHz bus rate the bus cycle is 62.5 ns and the 15 ns tPD leaves only 47.5 ns for address latch + memory access - often insufficient with commodity SRAM. Insert at least one wait state, or step up to the EP610LI-12 (12 ns tPD) for zero-wait-state designs. Also, the EPROM cell requires a minimum VCC ramp time during power-up; ensure VCC rises monotonically from 0 V to 4.75 V within 100 ms to avoid partial programming of unconfigured cells.
Estimated: The EP610LI-15's 3-state outputs drive TTL-level loads with a typical IOL of 24 mA and IOH of -4 mA. For bus-oriented designs, ensure that OE1 and OE2 are not asserted simultaneously by two devices - this creates bus contention and can damage the output stages. Add external pull-up resistors (4.7 kohm to 10 kohm) on shared bus lines to guarantee a defined logic state during contention windows. The CLK input should be driven by a buffered source (74LS04 or similar) rather than a long PCB trace, since the global clock feeds all 16 macrocells and is susceptible to skew.
Estimated: At maximum toggle rate (16 outputs at 83.3 MHz, 30 pF load), the EP610LI-15 dissipates approximately 500 mW - well within the ceramic DIP's 1 W rating. In static or low-frequency designs, ICC drops below 50 mA thanks to the CMOS process. Thermal management is generally not required in commercial-temperature applications; in industrial enclosures above +60C ambient, consider airflow or heatsink attachment to the ceramic body to maintain junction temperature below 150C derating limits.
Compliance Information
Ceramic side-brazed DIP package typically supplied with SnPb (tin-lead) finish - not RoHS compliant. For RoHS-compliant equivalents in the same family, choose EP610LC-15 (plastic DIP) or EP610DC-15. AEC-Q100 not applicable (legacy logic device, not automotive-qualified).
