EP610LC-15 - 16-Macrocell Classic EPLD, 15ns PLCC-28 | Altera
MPN: EP610LC-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.75 | $67.50 |
| 100 | $5.95 | $595.00 |
| 500 | $5.2 | $2,600.00 |
| 1,000 | $4.65 | $4,650.00 |
EP610LC-15 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that pre-dates modern FPGAs and CPLDs. In the taxonomy, an EPLD sits between a PAL (Programmable Array Logic) and a modern CPLD/FPGA: like a PAL, it is non-volatile and instant-on, but like a modern CPLD it contains multiple macrocells with sum-of-products logic and a fixed interconnect. The Classic EPLD family from Altera was widely adopted in the 1980s and 1990s as a higher-density, faster alternative to discrete PAL/GAL devices for state machines, address decoding, and bus-interface logic.
Key features of the EP610LC-15 include 16 macrocells with 16 dedicated flip-flops, propagation delays of 15 ns, fmax of 83.3 MHz counter frequency (and pipelined throughput up to 100 MHz), 24 input pins, and 16 output pins in the J-lead PLCC-28 footprint. The device operates from a single 5 V supply and is fabricated in CMOS technology, providing low static power consumption compared to bipolar PALs of the same era.
Architecturally, the EP610LC-15 uses a sum-of-products (AND-OR) plane feeding configurable macrocell flip-flops, with a global interconnect that guarantees deterministic, predictable timing - critical for synchronous state-machine design. This deterministic timing, plus non-volatile configuration, makes Classic EPLDs preferred over early FPGAs in safety- and timing-critical industrial applications. The device is currently maintained by Rochester Electronics, LLC as an authorized Altera licensee for long-lifecycle programs.
Typical applications include bus-interface glue logic, address decoding and chip-select generation, state-machine controllers, and replacement of discrete 74LS/74F TTL logic in 5 V systems. The wide operating voltage (single 5 V) and PLCC footprint also made it a common choice in industrial control, telecommunications backplane, and military/aerospace programs where long-term supply continuity is mandatory.
When designing with this device, note that programming requires a compatible EPROM/UV eraser and programmer (e.g., Data I/O or BP Microsystems), and design entry is typically performed with classic Altera MAX+PLUS II or equivalent tools. Designers should also verify available package alternatives (windowed ceramic vs. plastic OTP) before committing to a long-lifecycle design.
This page synthesizes Rochester Electronics distributor pricing, same-family Altera Classic drop-in alternatives, and practical design notes for long-lifecycle EPLD programs - information not consolidated in any single manufacturer datasheet.
Drop-in alternatives for EP610LC-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LC-15 (same form factor and footprint) β differing in Package, Operating Temperature, Family, Technology, Propagation Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610LC-20
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP610LC-25
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$6.2 / Unit
View Datasheet βEP610DC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP610IPC-25
β Drop-Inβ In Stock
$8.85 / Unit
View Datasheet βEP610DC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP610DC-30
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEP610LC-15 Maximum Ratings & Electrical Characteristics
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells |
| Equivalent Gates | 300 gates |
| Propagation Delay (tpd) | 15 ns |
| Counter Frequency (fmax) | 83.3 MHz |
| Pipelined Data Rate | up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) |
| Process Technology | CMOS |
| Package | 28-pin PLCC (J-lead, plastic OTP) |
| Mounting Type | Surface Mount |
| Number of Pins | 28 |
| Programming | OTP (one-time programmable) |
| RoHS Status | unknown |
EP610LC-15 Pin Configuration
| Pin 1 | IN1 β Dedicated input 1 |
| Pin 2 | IN2 β Dedicated input 2 |
| Pin 3 | IN3 β Dedicated input 3 |
| Pin 4 | IN4 β Dedicated input 4 |
| Pin 5 | IO1 β Macrocell I/O 1 (input or registered output) |
| Pin 6 | IO2 β Macrocell I/O 2 |
| Pin 7 | IO3 β Macrocell I/O 3 |
| Pin 8 | IO4 β Macrocell I/O 4 |
| Pin 9 | IO5 β Macrocell I/O 5 |
| Pin 10 | IO6 β Macrocell I/O 6 |
| Pin 11 | IO7 β Macrocell I/O 7 |
| Pin 12 | GND β Ground (per Altera Classic EPLD datasheet) |
| Pin 13 | IO8 β Macrocell I/O 8 |
| Pin 14 | IO9 β Macrocell I/O 9 |
| Pin 15 | IO10 β Macrocell I/O 10 |
| Pin 16 | IO11 β Macrocell I/O 11 |
| Pin 17 | IO12 β Macrocell I/O 12 |
| Pin 18 | IO13 β Macrocell I/O 13 |
| Pin 19 | IO14 β Macrocell I/O 14 |
| Pin 20 | IO15 β Macrocell I/O 15 |
| Pin 21 | IO16 β Macrocell I/O 16 |
| Pin 22 | IN5 β Dedicated input 5 |
| Pin 23 | IN6 β Dedicated input 6 |
| Pin 24 | IN7 β Dedicated input 7 |
| Pin 25 | VCC β +5V supply (per Altera Classic EPLD datasheet) |
| Pin 26 | NC β Not connected (per datasheet) |
| Pin 27 | NC β Not connected (per datasheet) |
| Pin 28 | NC β Not connected (per datasheet) |
Typical Applications
EP610LC-15 is suitable for 7 applications: Bus-Interface Glue Logic Replacement, Address Decoding and Chip-Select Generation, Synchronous State-Machine Controllers, Legacy Industrial Control and PLC I/O, Telecommunications Backplane Logic, Military and Aerospace Sustaining Programs, Replacement of Discontinued Bipolar PAL Devices.
Bus-Interface Glue Logic Replacement
The EP610LC-15 replaces 4-7 discrete 74LS/74F TTL or CMOS PAL/GAL packages in legacy 5 V bus-interface designs, where its 16 macrocells and 15 ns tpd handle address decoding, chip-select generation, and wait-state insertion in a single PLCC-28 device. Drop the EPLD into a 28-pin PLCC socket and consolidate what used to require a half-dozen MSI packages into one non-volatile part, reducing PCB area by 50-70% and eliminating socket-by-socket propagation-delay skew. The -15 ns grade is fast enough to keep up with 8-bit and 16-bit ISA, PC/104, and simple 68000/8086 bus cycles at full 8 MHz. Designers benefit from in-system design changes via UV-erase plus reprogramming in development, then move to the OTP commercial grade for production.
Recommended
Address Decoding and Chip-Select Generation
The EP610LC-15's 16 macrocells each implement sum-of-products logic with one flip-flop, making it ideal for address-decoding trees that need 8-12 active-low chip-select outputs for memory and peripheral banks. With 24 input pins and 16 I/O pins, the device can absorb a 24-bit address bus and emit up to 16 individually-decoded chip selects in a single pass, replacing 3-4 cascaded 74LS138/PAL16L8 decoder chains. The 15 ns tpd keeps the decoded output within one 5 V clock cycle for 8-bit systems at 25 MHz, and the deterministic timing simplifies worst-case timing analysis. Rochester Electronics continues to supply the part for sustaining long-lifecycle industrial controllers that depend on this exact decoding pattern.
Recommended
Synchronous State-Machine Controllers
The EP610LC-15 hosts 4-8 medium-complexity synchronous state machines (8-32 states each) in a single 28-pin PLCC, with each macrocell's dedicated D-flip-flop and sum-of-products plane implementing one Mealy or Moore state register. At 15 ns tpd and 83.3 MHz counter fmax, the part clocks reliably up to 33 MHz on the registered outputs and runs pipelined logic at 100 MHz, comfortably handling V.24, HDLC, and simple UART state machines at standard baud rates. The non-volatile configuration means the controller powers up in a known state on every cold start - critical for safety interlocks and industrial PLC sequencers that cannot tolerate FPGA configuration latency.
Recommended
Legacy Industrial Control and PLC I/O
Long-lifecycle industrial controllers, PLCs, and CNC machine interfaces originally designed in the late 1980s and 1990s use the EP610LC-15 as the main glue-logic device on 5 V ISA and STD-bus backplanes, where its -40C to +85C industrial-temperature EP610IPC variant handles harsh factory environments. Rochester Electronics' licensed reproduction program guarantees 10-20 year supply continuity for these programs that cannot be re-engineered onto a MAX II CPLD without re-qualifying the entire controller. The deterministic 15 ns timing allows the controller to deterministically service opto-isolated 24 V digital inputs and solid-state relay outputs within a 1 ms scan cycle.
Recommended
Telecommunications Backplane Logic
The EP610LC-15 provides non-volatile glue logic on 5 V telecommunications backplanes for T1/E1 line cards, channel banks, and central-office switching equipment, where its CMOS process and 15 ns timing handle framing, alarm monitoring, and bus arbitration between 8-16 line-interface cards. The 300-gate capacity is well-matched to mid-complexity per-card logic, and the PLCC-28 footprint fits the 0.1 inch grid backplane standard of the era. Telco-grade programs require 20+ year part availability, which Rochester Electronics' authorized Altera license guarantees for EP610-series EPLDs in active deployed systems.
Recommended
Military and Aerospace Sustaining Programs
Avionics, military radio, and aerospace test equipment designed with EP610-series EPLDs in the 1990s are still in service today, and the EP610DM/883B (DESC-processed ceramic DIP) and EP610LC-15 commercial variants continue to be supplied by Rochester Electronics for these long-lifecycle programs. Designers benefit from the device's deterministic timing, radiation-tolerant CMOS process, and MIL-STD-883 screening options. For new military designs, however, leaded Altera MAX II or Microsemi (formerly Actel) ProASIC3 FPGAs are preferred due to their modern radiation-hardness assurance flow and ITAR/EAR export compliance.
Recommended
Replacement of Discontinued Bipolar PAL Devices
The EP610LC-15 directly replaces obsolete bipolar PAL16L8, PAL20L8, PAL22V10, and PAL20X10 devices in legacy 5 V designs that need higher density than a single PAL but where a modern CPLD is overkill. With 16 macrocells (vs. 8-10 in a PAL22V10), the EP610LC-15 absorbs 2-3 PAL functions in one PLCC-28, and the CMOS process reduces quiescent current from 100-200 mA (bipolar PAL) to under 50 mA. The 15 ns tpd matches the speed of the fastest bipolar PALCE22V10-15 parts, making the migration transparent at the timing level. Designers moving from bipolar PALs to the EP610LC-15 also gain the advantage of design re-programmability during development.
Recommended
Recommended Products Summary
Engineering reference data for EP610LC-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LC-20 | EP610LC-25 | EP610DC-15 | EP610IPC-25 | EP610DC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) | Altera (Rochester Electronics) |
| Package | PLCC-28 (J-lead) | PLCC-28 (J-lead) - same | PLCC-28 (J-lead) - same | CERDIP-28 (DIP form factor) | PDIP-24 (24 pins, different) | CERDIP-28 (DIP form factor) |
| Propagation Delay (tpd) | 15 ns | 20 ns | 25 ns | 15 ns (same) | 25 ns | 25 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Equivalent Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Counter Frequency (fmax) | 83.3 MHz | 62.5 MHz | 50 MHz | 83.3 MHz | 50 MHz | 50 MHz |
| Temperature Grade | Commercial (0C to 70C) | Commercial (0C to 70C) | Commercial (0C to 70C) | Commercial (0C to 70C) | Industrial (-40C to 85C) | Commercial (0C to 70C) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programming | OTP (one-time programmable) | OTP | OTP | Windowed UV-erase / OTP | OTP | Windowed UV-erase / OTP |
Key Differentiators
- Fastest speed grade in the EP610 Classic EPLD PLCC-28 family (vs EP610LC-20)
- Plastic PLCC-28 commercial-grade OTP package (vs EP610DC-15)
- J-lead PLCC surface-mount form factor (vs EP610IPC-25 (PDIP-24))
- Authorized licensed reproduction by Rochester Electronics (vs Broker / secondary-market EP610LC-15)
Design Notes
The EP610LC-15 is OTP (one-time programmable) and cannot be re-programmed in-circuit or with JTAG - a programming error destroys the part. During development, use a windowed ceramic DIP variant (EP610DC-15) or a UV-erasable PLCC equivalent so you can erase with a 30-minute UV exposure and re-program. For production programming, use a Data I/O Model 29B or BP Microsystems programmer with the Altera MAX+PLUS II (classic) software - Quartus Prime does NOT support Classic EPLDs.
The EP610LC-15 is a CMOS Classic EPLD with typical quiescent current under 50 mA at 5V, but transient supply current during simultaneous-macrocell switching can spike to 200-300 mA. Decouple VCC (pin 25) with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a 10 uF tantalum bulk capacitor on the same 5 V rail. The device has no power-on-reset - macrocell flip-flops power up in an undefined state, so design your state machine to enter a known initial state on the first clock edge after VCC crosses 4.0 V.
PLCC-28 sockets (JEDEC-standard 0.05 inch pitch) are recommended for development and field-serviceable production to allow device replacement. If surface-mounting the EP610LC-15 directly to the PCB, use JEDEC PLCC-28 land pattern with solder mask defined pads (SMD) per IPC-7351, and follow standard reflow profile with peak temperature 245C for 20 seconds (JEDEC J-STD-020 MSL-3 handling for plastic OTP packages). Hand-soldering the J-leads is feasible with a fine-tip iron but verify each lead with magnification to avoid cold joints.
Estimated: with 15 ns tpd and 5 V CMOS output drive (4 mA IOL/IOH typical), the EP610LC-15 can drive a 50 pF load with rise/fall times under 8 ns - well below the 15 ns propagation delay. For bus-interface applications, fan-out is limited to 10-20 LSTTL loads per output pin due to CMOS drive strength; for heavier loads, buffer with 74LS245 or 74FCT245 transceivers. Unused dedicated inputs (IN1-IN7) must be tied to VCC or GND through 10 kohm resistors to prevent floating-input oscillation that increases ICC and can trigger spurious macrocell transitions.
Compliance Information
The original Altera Classic EPLD family was introduced before RoHS/REACH standardization; Rochester Electronics authorized reproduction part status depends on specific lot date code. Use Rochester Electronics' per-part compliance certificate for current RoHS/REACH information.
