EPC16UI88N - 16Mb In-System Prog Config PROM 88-UBGA | Intel
MPN: EPC16UI88N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22 | $2,200.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $17.8 | $17,800.00 |
EPC16UI88N Overview
What is a configuration PROM? A configuration PROM is a non-volatile memory device that stores the bitstream for an FPGA. At power-up or under user control, the PROM serially or in parallel transfers the bitstream to the target FPGA through a dedicated configuration interface (such as Altera's PS, FPP, or AS modes). Configuration PROMs are part of the broader memory hierarchy: PROM -> non-volatile memory -> memory IC -> integrated circuit. They differ from boot flash in microcontrollers because they speak FPGA-specific protocols and include features like multi-device cascading, decompression, and in-system programming (ISP) via JTAG.
Key features of the EPC16UI88N include 16 Mbit density, in-system programmability through IEEE 1149.1 (JTAG), a 3.3 V single-supply core, an industrial operating temperature range of -40 C to +85 C, and built-in support for configuring multiple FPGAs in a daisy chain. The device integrates a flash memory array with a configuration controller on a single die, eliminating the need for external memory. The 88-ball UFBGA package supports high-density routing and is suitable for space-constrained designs.
Architecturally, the EPC16 uses a flash-based memory core instead of older EPROM or EEPROM cells, allowing unlimited reconfiguration cycles through JTAG. A configuration controller block manages the serial/parallel data transfer and handles multi-device daisy chaining automatically, simplifying board design when several FPGAs must be loaded from a single chain.
Typical applications include configuring Altera Stratix, Cyclone, and APEX series FPGAs in industrial control, telecommunications, and test equipment. The device is also used in prototype development where bitstreams are updated frequently via JTAG. When designing with this part, ensure the configuration clock routing on the PCB is short and matched to avoid signal-integrity issues, and respect the cascade-mode timing when multiple EPC16 devices share a chain.
Drop-in alternatives for EPC16UI88N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC16UI88N (same form factor and footprint) — differing in Package, Memory Type, Memory Size, Operating Temperature, Configuration Interface.
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View Datasheet →EPC16UI88N Maximum Ratings & Electrical Characteristics
| Memory Type | In-System Programmable Configuration PROM |
| Memory Size | 16 Mbit (2 Mbyte) |
| Programmable Type | In System Programmable |
| Supply Voltage - Operating | 3.3 V |
| Supply Voltage Range | 2.25 V to 6 V (per GlobalSpec) |
| Configuration Clock Frequency | 66.7 MHz max |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Package / Case | 88-UBGA / UFBGA (11 mm x 8 mm) |
| Mounting Type | Surface Mount |
| Family | EPC16 |
| Interface | Serial / JTAG (IEEE 1149.1) |
| Number of Terminals | 88 |
| Package Code | FBGA |
EPC16UI88N fbga Pin Configuration Guide
Pin configuration for EPC16UI88N (fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPC16UI88N.
Refer to the datasheet for full pin configuration.
Typical Applications
EPC16UI88N is suitable for 7 applications: Stratix FPGA Configuration Storage, Cyclone FPGA Boot Memory, Telecom Base Station FPGA Configuration, Test & Measurement Instrumentation, Industrial Control & Factory Automation, Multi-FPGA Daisy-Chain Configuration Master, Legacy Avionics & Defense Systems.
Stratix FPGA Configuration Storage
The EPC16UI88N stores the configuration bitstream for Altera Stratix-series FPGAs in industrial designs. Its 16 Mbit density is well-matched to large Stratix EP1S25/EP1S40 bitstreams, and the 66.7 MHz configuration clock minimizes FPGA boot time to roughly 250 ms for a full 2 Mbyte image. According to Altera's Enhanced Configuration Devices datasheet, the EPC16UI88N supports daisy-chaining multiple FPGAs from a single PROM, eliminating the need for a separate boot flash per device. The industrial -40 C to +85 C rating allows deployment in factory-floor controllers and outdoor telecom equipment.
Recommended
Cyclone FPGA Boot Memory
The EPC16UI88N serves as the boot memory for Altera Cyclone EP1C6/EP1C12 FPGAs in cost-sensitive industrial products. The 16 Mbit density exceeds the bitstream size of mid-range Cyclone devices, leaving room for multiple bitstreams for in-field upgrades through the JTAG port. The in-system programmability allows manufacturers to update firmware without removing the board. Because the EPC16UI88N operates from a single 3.3 V rail, it interfaces directly to the Cyclone's 3.3 V configuration pins without level shifters, simplifying PCB layout.
Recommended
Telecom Base Station FPGA Configuration
In telecom base stations the EPC16UI88N configures DSP-capable Altera FPGAs that handle baseband processing. The industrial temperature grade ensures reliable operation in outdoor enclosures and unconditioned shelters, while the 16 Mbit density supports bitstreams for Stratix II DSP variants used in early 4G baseband designs. The JTAG interface enables remote bitstream updates for protocol upgrades. Combined with the 66.7 MHz configuration clock, the EPC16UI88N meets telecom carrier-grade requirements for fast reboot after power-cycle events.
Recommended
Test & Measurement Instrumentation
Test-and-measurement instruments such as oscilloscopes, logic analyzers, and protocol testers use the EPC16UI88N to configure the Altera FPGAs that handle high-speed data acquisition. The 16 Mbit capacity accommodates the largest logic-analyzer bitstreams, while the in-system programmability allows field updates when new protocol decoders are released. Designers appreciate the JTAG interface because it shares pins with the FPGA's JTAG chain, simplifying board bring-up and boundary-scan test. The 88-ball UFBGA is small enough for handheld and benchtop instruments.
Recommended
Industrial Control & Factory Automation
Factory-automation controllers and PLCs use the EPC16UI88N to configure Altera APEX or Cyclone FPGAs that handle deterministic real-time I/O. The industrial -40 C to +85 C rating is essential for cabinets near motors and heaters, where ambient temperature can exceed 60 C. The flash-based core allows unlimited reconfiguration cycles when control firmware is updated, supporting Industry 4.0 use cases where machine behavior is re-programmed for new product runs. The single 3.3 V supply integrates cleanly with industrial 24V-to-3.3V DC-DC rails.
Recommended
Multi-FPGA Daisy-Chain Configuration Master
The EPC16UI88N can act as the master device in a daisy-chain configuration of multiple Altera FPGAs. Per the Altera datasheet, the configuration controller automatically handles the cascade handshake, so a single EPC16 can feed bitstreams to 2-4 FPGAs sequentially. This saves board area and cost compared with one PROM per FPGA. The 16 Mbit capacity accommodates the combined bitstream of small-to-medium FPGAs such as Cyclone II and Cyclone III families, which are common in legacy industrial and embedded products.
Recommended
Legacy Avionics & Defense Systems
The EPC16UI88N is found in legacy avionics and defense subsystems where Altera APEX and early Stratix FPGAs perform signal processing. The industrial temperature grade, combined with Altera's MIL-PRF-38535 screening option, suits many line-replaceable units (LRUs). Because the part is obsolete, defense integrators maintain long-term inventory contracts with specialty distributors and qualify the EPC16UC88 family as a secondary source. Designers of new defense systems should evaluate modern Stratix-V or Cyclone-V based configuration solutions instead.
Recommended
Recommended Products Summary
Engineering reference data for EPC16UI88N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16UI88AA | EPC16UI88 | EPC16UC88N | EPC16UC88AA | EPC16UC88AB | EPC16UC88 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 88-UBGA (11x8) | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same |
| Memory Size | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit | 16 Mbit |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C | -40 C to +85 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Config Clock Max | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz |
| Programmability | In-System (JTAG) | In-System (JTAG) | In-System (JTAG) | In-System (JTAG) | In-System (JTAG) | In-System (JTAG) | In-System (JTAG) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade (-40 C to +85 C) (vs EPC16UC88N)
- 16 Mbit density for very-high-density FPGAs (vs EPC8)
- 66.7 MHz configuration clock speed (vs EPC2)
Design Notes
Place 0.1 uF X7R decoupling capacitors within 3 mm of every VCC ball on the 88-ball UFBGA, and a single 10 uF tantalum bulk capacitor near the package's power balls. Use NSMD (non-solder mask defined) pads with via-in-pad for the inner balls to reduce inductance. Route configuration clock (DCLK) and data (DATA[7:0]) as matched-length traces within 100 mils of the target FPGA's configuration pins; impedance should be 50 ohm single-ended to a 3.3 V reference plane.
For daisy-chain configurations, place the EPC16UI88N physically adjacent to the first FPGA and keep the cascade traces (nCS, nSTATUS, CONF_DONE) short and matched. The Altera datasheet specifies a maximum cascade-frequency de-rating when chaining more than two FPGAs; verify with the latest timing tables. Provide a JTAG header with TDI, TDO, TMS, TCK, and GND on every board for in-system reprogramming and boundary-scan testing - this also supports post-assembly bitstream updates in the field.
The 88-ball UFBGA package places VCC and GND balls on the inner rows, which means all power enters through the BGA's center. Use a power plane on an adjacent layer stitched with vias directly under the package to minimize inductance. Series-terminate the DCLK line near the FPGA side with a 33 ohm resistor if the configuration clock trace exceeds 50 mm. Series-terminate DATA lines only when the FPGA pins do not have internal weak pull-downs enabled by default in the Quartus device configuration.
Do not assume the EPC16UI88N can be hot-swapped with newer EPCQ-series devices - the EPC16 uses Altera's legacy 3.3 V parallel/serial interface while the EPCQ uses 1.8 V/2.5 V/3.3 V quad-serial SPI. The two are NOT pin-compatible. Also, when migrating from industrial grade (EPC16UI88N) to commercial grade (EPC16UC88N) for cost savings, re-validate thermal margin in your worst-case operating environment - the 70 C ceiling of the commercial part is exceeded in many outdoor enclosures.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-mineral compliance were not present in the verified web data. Marked as unknown per data authenticity rules. The part is obsolete / last-time-buy and was originally released before mandatory RoHS-6 reporting; check the lot-specific CoC when sourcing from brokers.
