EPC1LC20/LI20 - Altera 1Mb OTP Configuration PROM | PLCC-20
MPN: EPC1LC20/LI20 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.4 | $74.00 |
| 100 | $6.2 | $620.00 |
| 500 | $5.3 | $2,650.00 |
| 1,000 | $4.6 | $4,600.00 |
EPC1LC20/LI20 Overview
An Altera Configuration PROM is a non-volatile memory device specifically designed to store the configuration bitstream of an SRAM-based FPGA. Because SRAM FPGAs lose their configuration when power is removed, they require an external boot memory to reload their logic fabric and routing on every power-up. Altera's EPC1 series pre-dates modern flash-based solutions such as EPCS and EPCQ, and uses a proprietary serial daisy-chain interface (not SPI-compatible). The /LI20 suffix designates the industrial operating temperature grade, qualified for -40C to +85C operation.
Key features include 3.3V and 5.0V in-system programmability (ISP) through the built-in IEEE 1149.1 JTAG interface, a low-power CMOS process, and a maximum configuration clock rate compatible with legacy APEX 20K FPGAs. The PLCC-20 package is socket-compatible, allowing easy in-system replacement and programming.
The EPC1LC20 uses Altera's proprietary serial configuration protocol, not the industry-standard SPI interface found in later EPCS devices. This protocol uses the nSTATUS, CONF_DONE, and DCLK handshaking signals, allowing the PROM to control FPGA configuration timing autonomously. A single EPC1 can cascade to configure multiple FPGAs in daisy-chain mode.
Typical applications include APEX 20K-series FPGA boot memory, FLEX 10K-series configuration storage, ACEX 1K-family boot loading, and industrial embedded systems requiring -40C to +85C temperature range operation. The EPC1LC20/LI20 is suitable for legacy designs and field-programmable industrial controllers.
When designing with this device, note that it cannot be replaced by EPCS-series PROMs without firmware changes, because the EPCS family uses SPI protocol while EPC1 uses the older Altera serial protocol. Designers migrating from APEX 20K to Cyclone or newer FPGA families must also migrate to EPCS or EPCQ configuration PROMs.
This page synthesizes distributor pricing, drop-in same-package alternatives, and protocol-level design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPC1LC20/LI20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1LC20/LI20 (same form factor and footprint) — differing in Package, Memory Type, Compatible FPGA Families, Operating Temperature, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1441LC20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC1441LC20N
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20-W
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPC1LC20-WCEC52
✅ Drop-In✓ In Stock
$7.45 / Unit
View Datasheet →EPC1LC20/LI20 Maximum Ratings & Electrical Characteristics
| Memory Type | OTP Configuration PROM |
| Memory Size | 1 Mbit |
| Interface | Altera proprietary serial (not SPI) |
| Maximum Configuration Clock | 8 MHz |
| Supply Voltage | 3.3 V / 5.0 V |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG |
| Package | 20-pin PLCC (J-lead) |
| Operating Temperature | -40 C to +85 C (industrial grade) |
| Mounting Type | Surface Mount |
| Compatible FPGA Families | APEX 20K, FLEX 10K, ACEX 1K |
| Cascade Support | Yes (daisy-chain to multiple FPGAs) |
| Process Technology | CMOS |
| Programmability | One-Time Programmable (OTP) |
EPC1LC20/LI20 Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA DATA0 |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nSTATUS — Configuration status handshaking signal |
| Pin 4 | OE — Output enable for configuration data |
| Pin 5 | nCASC — Daisy-chain cascade output |
| Pin 6 | nCONFIG — Configuration initiate input |
| Pin 7 | VCC — Power supply (3.3V or 5.0V) |
| Pin 8 | TDI — JTAG Test Data In |
| Pin 9 | TMS — JTAG Test Mode Select |
| Pin 10 | TCK — JTAG Test Clock |
| Pin 11 | GND — Ground reference |
| Pin 12 | TDO — JTAG Test Data Out |
| Pin 13 | nCE — Chip Enable (active low) |
| Pin 14 | CONF_DONE — Configuration complete status output |
| Pin 15 | VCC — Power supply pin |
| Pin 16 | GND — Ground pin |
| Pin 17 | VPP — Programming voltage supply |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | RESERVED — Reserved per datasheet, leave open |
Typical Applications
EPC1LC20/LI20 is suitable for 6 applications: APEX 20K FPGA Configuration Boot Memory, FLEX 10K Family Configuration Storage, ACEX 1K FPGA Boot Loading, Industrial Embedded Control Systems, Multi-FPGA Daisy-Chain Configuration, Legacy Test and Measurement Equipment.
APEX 20K FPGA Configuration Boot Memory
The EPC1LC20/LI20 was designed as the primary configuration memory for Altera APEX 20K-series FPGAs, which require an external boot PROM because their SRAM-based logic fabric loses configuration when power is removed. The 1 Mbit capacity matches the typical APEX 20K bitstream size, and the 8 MHz configuration clock enables full device boot within tens of milliseconds. The Altera proprietary serial protocol with nSTATUS/CONF_DONE/DCLK handshaking ensures robust configuration timing even in noisy industrial environments. Designers should size the PROM with 10-20% headroom over the FPGA bitstream to accommodate engineering revisions.
Recommended
FLEX 10K Family Configuration Storage
For FLEX 10K and FLEX 10KE FPGAs, the EPC1LC20/LI20 provides non-volatile storage of the configuration bitstream at 1 Mbit capacity, suitable for smaller FLEX 10K devices. The 8 MHz maximum configuration clock allows rapid boot, critical in systems with tight power-on-to-functional timing requirements. The PLCC-20 surface-mount package supports standard pick-and-place assembly, and the JTAG-based in-system programming enables factory and field firmware updates without removing the PROM from the board. Industrial-grade temperature operation suits factory automation applications.
Recommended
ACEX 1K FPGA Boot Loading
The EPC1LC20/LI20 supports ACEX 1K-family FPGAs as a configuration source, providing reliable bitstream storage for these low-cost, high-volume SRAM-based devices. The Altera proprietary serial interface with nSTATUS, CONF_DONE, and DCLK handshaking ensures deterministic configuration start-up. ACEX 1K devices typically fit within the 1 Mbit capacity, making the EPC1LC20 an economical choice. The industrial temperature grade allows deployment in factory-floor and outdoor enclosures where temperatures can range from -40C to +85C.
Recommended
Industrial Embedded Control Systems
In industrial embedded controllers built around Altera APEX 20K or FLEX 10K FPGAs, the EPC1LC20/LI20 provides rugged industrial-temperature operation (-40C to +85C) with reliable boot behavior. The PLCC-20 package can be socketed for easy field replacement in legacy industrial installations, supporting decades-long service life requirements common in factory automation. The JTAG programming interface allows on-site firmware updates during commissioning or maintenance cycles. Combined with the Altera proprietary configuration protocol, the EPC1LC20/LI20 offers predictable power-on behavior critical for process-control applications.
Recommended
Multi-FPGA Daisy-Chain Configuration
The EPC1LC20/LI20 supports daisy-chain configuration of multiple Altera FPGAs through its nCASC pin, allowing one PROM to boot an entire chain of APEX 20K or FLEX 10K devices sequentially. This is useful in high-density designs where multiple FPGAs share a common bitstream or where FPGA-to-FPGA configuration propagation simplifies board layout. The Altera proprietary serial protocol with CONF_DONE feedback ensures each FPGA in the chain signals successful configuration before the next device begins. Industrial temperature operation enables deployment in outdoor telecommunications and process-control installations.
Recommended
Legacy Test and Measurement Equipment
Long-life test-and-measurement instruments built around Altera APEX 20K or FLEX 10K FPGAs continue to use the EPC1LC20/LI20 as their configuration memory because it remains in distributor inventory while newer SPI-based EPCS devices require firmware changes. The industrial temperature grade suits lab and field environments. JTAG programming allows calibration data and test routines to be updated via standard boundary-scan tools. The 20-pin PLCC socket form factor is widely supported by test fixtures and legacy programming adapters used in production-line testing.
Recommended
Recommended Products Summary
Engineering reference data for EPC1LC20/LI20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC1441LC20 | EPC1441LC20N | EPC1LC20-W |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Size | 1 Mbit | 1 Mbit - same | ~4 Mbit - larger | ~4 Mbit - larger | 1 Mbit - same |
| Configuration Clock | 8 MHz | 8 MHz - same | 8 MHz - same | 8 MHz - same | 8 MHz - same |
| Interface Protocol | Altera proprietary serial | Altera proprietary serial - same | Altera proprietary serial - same | Altera proprietary serial - same | Altera proprietary serial - same |
| Compatible FPGAs | APEX 20K, FLEX 10K, ACEX 1K | APEX 20K, FLEX 10K, ACEX 1K - same | APEX 20K, FLEX 10K, ACEX 1K - same | APEX 20K, FLEX 10K, ACEX 1K - same | APEX 20K, FLEX 10K, ACEX 1K - same |
| In-System Programming | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) - same | JTAG (IEEE 1149.1) - same | JTAG (IEEE 1149.1) - same | JTAG (IEEE 1149.1) - same |
Key Differentiators
- Industrial temperature grade in identical PLCC-20 footprint (vs EPC1LC20)
- Larger memory density upgrade path in same package (vs EPC1441LC20)
- Altera proprietary serial protocol lock-in (vs EPCS1)
Design Notes
The EPC1LC20/LI20 uses Altera proprietary serial protocol with nSTATUS, CONF_DONE, and DCLK as critical handshaking signals between the PROM and FPGA. According to the manufacturer datasheet, route DCLK as a single-ended signal kept short (under 50 mm) and shield the configuration clock trace from switching power nodes to prevent ground-bounce induced configuration failures. Add a 100 ohm series termination near the FPGA DCLK pin if the trace exceeds 25 mm to suppress ringing. Ensure nSTATUS and CONF_DONE have external pull-up resistors as specified by the Altera Configuration Devices handbook, since these are open-drain signals.
Engineers migrating from APEX 20K or FLEX 10K to Cyclone, Stratix, or Arria families must also migrate the configuration PROM from EPC1 (Altera proprietary serial) to EPCS or EPCQ (SPI/quad-SPI). Per the Altera migration guide, the EPC1 cannot directly replace an EPCS device because the FPGA's configuration controller firmware expects SPI protocol commands, not the legacy nSTATUS/CONF_DONE/DCLK handshaking. Attempting this substitution results in configuration failure with nSTATUS held low after power-up. Always confirm both the FPGA family and the configuration PROM support the same protocol before PCB layout.
The EPC1LC20/LI20 in a 20-pin PLCC package has modest power dissipation during read operation (under 50 mW typical) but JTAG programming can draw higher currents with VPP active. Per the manufacturer datasheet, the industrial -40C to +85C temperature range is supported without heatsinking in typical applications. However, when programming in-system with VPP=12V, ensure the surrounding board temperature stays within the datasheet maximum of +85C, as VPP-induced junction heating combined with elevated ambient can exceed the rating. Estimated: VPP=12V at 50 mA programming current yields 600 mW additional dissipation - manageable but monitor thermal envelope.
Compliance Information
RoHS/REACH/lead-free status not confirmed in the verified web data; original Altera datasheet predates widespread RoHS documentation. Marked [DATA_NEEDED] in specs where applicable. AEC-Q100 is not_applicable because this is a memory/configuration device, not an automotive analog/power IC.
